RDMA/hns: Modify qp&cq&pd specification according to UM

Accroding to hip08's limitation, qp&cq specification is 1M, mtpt
specification 1M in kernel space.

Signed-off-by: Yangyang Li <liyangyang20@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 6b0486f..f1f1b75 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -45,14 +45,14 @@
 #define HNS_ROCE_VF_SGID_NUM                   32
 #define HNS_ROCE_VF_SL_NUM                     8
 
-#define HNS_ROCE_V2_MAX_QP_NUM                 0x2000
-#define HNS_ROCE_V2_MAX_QPC_TIMER_NUM          0x200
+#define HNS_ROCE_V2_MAX_QP_NUM                 0x100000
+#define HNS_ROCE_V2_MAX_QPC_TIMER_NUM          0x200
 #define HNS_ROCE_V2_MAX_WQE_NUM                        0x8000
 #define        HNS_ROCE_V2_MAX_SRQ                     0x100000
 #define HNS_ROCE_V2_MAX_SRQ_WR                 0x8000
 #define HNS_ROCE_V2_MAX_SRQ_SGE                        0x100
-#define HNS_ROCE_V2_MAX_CQ_NUM                 0x8000
-#define HNS_ROCE_V2_MAX_CQC_TIMER_NUM          0x100
+#define HNS_ROCE_V2_MAX_CQ_NUM                 0x100000
+#define HNS_ROCE_V2_MAX_CQC_TIMER_NUM          0x100
 #define HNS_ROCE_V2_MAX_SRQ_NUM                        0x100000
 #define HNS_ROCE_V2_MAX_CQE_NUM                        0x10000
 #define HNS_ROCE_V2_MAX_SRQWQE_NUM             0x8000
@@ -67,7 +67,7 @@
 #define HNS_ROCE_V2_COMP_VEC_NUM               63
 #define HNS_ROCE_V2_AEQE_VEC_NUM               1
 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM           1
-#define HNS_ROCE_V2_MAX_MTPT_NUM               0x8000
+#define HNS_ROCE_V2_MAX_MTPT_NUM               0x100000
 #define HNS_ROCE_V2_MAX_MTT_SEGS               0x1000000
 #define HNS_ROCE_V2_MAX_CQE_SEGS               0x1000000
 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS            0x1000000