}
}
+void HexagonDAGToDAGISel::ppEmitAligna() {
+ auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
+ auto &HFI = *HST.getFrameLowering();
+ if (!HFI.needsAligna(*MF))
+ return;
+
+ MachineFrameInfo &MFI = MF->getFrameInfo();
+ MachineBasicBlock &EntryBB = MF->front();
+ unsigned AR = FuncInfo->CreateReg(MVT::i32);
+ unsigned MaxA = MFI.getMaxAlignment();
+ MachineBasicBlock::iterator End = EntryBB.end();
+ DebugLoc DL = EntryBB.findDebugLoc(End);
+ BuildMI(EntryBB, End, DL, HII->get(Hexagon::PS_aligna), AR)
+ .addImm(MaxA);
+ MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
+}
+
void HexagonDAGToDAGISel::PreprocessISelDAG() {
// Repack all nodes before calling each preprocessing function,
// because each of them can modify the set of nodes.
CurDAG->dump();
});
}
-}
-
-void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
- auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
- auto &HFI = *HST.getFrameLowering();
- if (!HFI.needsAligna(*MF))
- return;
- MachineFrameInfo &MFI = MF->getFrameInfo();
- MachineBasicBlock *EntryBB = &MF->front();
- unsigned AR = FuncInfo->CreateReg(MVT::i32);
- unsigned MaxA = MFI.getMaxAlignment();
- BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)
- .addImm(MaxA);
- MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
+ // Finally, emit the PS_aligna instruction, if necessary. Do it late,
+ // because the max required stack layout may change up until right before
+ // instruction selection.
+ ppEmitAligna();
}
// Match a frame index that can be used in an addressing mode.
return true;
}
void PreprocessISelDAG() override;
- void EmitFunctionEntryCode() override;
-
void Select(SDNode *N) override;
// Complex Pattern Selectors.
void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
+ void ppEmitAligna();
SmallDenseMap<SDNode *,int> RootWeights;
SmallDenseMap<SDNode *,int> RootHeights;