drm/i915: Query the vswing levels per-lane for snps phy

Prepare for per-lane drive settings by querying the desired vswing
level per-lane.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-12-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 5e20f34..c225121 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -58,7 +58,6 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        const struct intel_ddi_buf_trans *trans;
        enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-       int level = intel_ddi_level(encoder, crtc_state, 0);
        int n_entries, ln;
 
        trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
@@ -66,6 +65,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
                return;
 
        for (ln = 0; ln < 4; ln++) {
+               int level = intel_ddi_level(encoder, crtc_state, ln);
                u32 val = 0;
 
                val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);