[Hexagon] Enforce restrictions on packetizing cache instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335061 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index e44c723..ae97471 100644 (file)
--- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1115,6 +1115,10 @@ static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
   case Hexagon::S4_stored_locked:
   case Hexagon::L2_loadw_locked:
   case Hexagon::L4_loadd_locked:
+  case Hexagon::Y2_dccleana:
+  case Hexagon::Y2_dccleaninva:
+  case Hexagon::Y2_dcinva:
+  case Hexagon::Y2_dczeroa:
   case Hexagon::Y4_l2fetch:
   case Hexagon::Y5_l2fetch: {
     // These instructions can only be grouped with ALU32 or non-floating-point

diff --git a/test/CodeGen/Hexagon/packetize-dccleana.mir b/test/CodeGen/Hexagon/packetize-dccleana.mir
new file mode 100644 (file)
index 0000000..a26fabd
--- /dev/null
+++ b/test/CodeGen/Hexagon/packetize-dccleana.mir
@@ -0,0 +1,16 @@
+# RUN: llc -march=hexagon -run-pass=hexagon-packetizer -o - %s | FileCheck %s
+
+# Make sure that the load is not packetized together with the dccleana.
+# CHECK-NOT: BUNDLE
+
+---
+name: foo
+tracksRegLiveness: true
+fixedStack:
+- { id: 0, offset: 0, size: 16, alignment: 8, isImmutable: true }
+body: |
+  bb.0:
+    liveins: $r1
+    Y2_dccleana killed renamable $r1
+    $d8 = L2_loadrd_io killed $r29, 8 :: (load 8 from %fixed-stack.0)
+...