tests/tcg/xtensa: add test for failed memory transactions

Failed memory transactions should raise exceptions 14 (for fetch) or 15
(for load/store) with XEA2.

Memory accesses that result in TLB miss followed by an attempt to load
PTE from physical memory which fails should raise InstTLBMiss or
LoadStoreTLBMiss with XEA2.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile
index 091518c..2f5691f 100644 (file)
--- a/tests/tcg/xtensa/Makefile
+++ b/tests/tcg/xtensa/Makefile
@@ -44,6 +44,7 @@ TESTCASES += test_mmu.tst
 TESTCASES += test_mul16.tst
 TESTCASES += test_mul32.tst
 TESTCASES += test_nsa.tst
+TESTCASES += test_phys_mem.tst
 ifdef XT
 TESTCASES += test_pipeline.tst
 endif

diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S
new file mode 100644 (file)
index 0000000..aae0a79
--- /dev/null
+++ b/tests/tcg/xtensa/test_phys_mem.S
@@ -0,0 +1,124 @@
+#include "macros.inc"
+
+test_suite phys_mem
+
+.purgem test_init
+
+.macro test_init
+    movi    a2, 0xc0000003 /* PPN */
+    movi    a3, 0xc0000004 /* VPN */
+    wdtlb   a2, a3
+    witlb   a2, a3
+    movi    a2, 0xc0000000
+    wsr     a2, ptevaddr
+.endm
+
+test inst_fetch_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+    jx      a2
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 16
+    assert  eq, a2, a3
+test_end
+
+test read_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+1:
+    l32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 24
+    assert  eq, a2, a3
+test_end
+
+test write_get_pte_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0x20000000
+1:
+    s32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0x20000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 24
+    assert  eq, a2, a3
+test_end
+
+test inst_fetch_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+    jx      a2
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 14
+    assert  eq, a2, a3
+test_end
+
+test read_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+1:
+    l32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 15
+    assert  eq, a2, a3
+test_end
+
+test write_no_phys
+    set_vector kernel, 2f
+
+    movi    a2, 0xc0000000
+1:
+    s32i    a3, a2, 0
+    test_fail
+2:
+    movi    a2, 0xc0000000
+    rsr     a3, excvaddr
+    assert  eq, a2, a3
+    movi    a2, 1b
+    rsr     a3, epc1
+    assert  eq, a2, a3
+    rsr     a3, exccause
+    movi    a2, 15
+    assert  eq, a2, a3
+test_end
+
+test_suite_end