reg testbench updated.

diff --git a/simulation/cpu/testbench_regn.vhd b/simulation/cpu/testbench_regn.vhd
index 8d3243b..4fbcb04 100644 (file)
--- a/simulation/cpu/testbench_regn.vhd
+++ b/simulation/cpu/testbench_regn.vhd
@@ -17,7 +17,7 @@ architecture stimulus of testbench_regn is
                 q           : out std_logic_vector (dsize - 1 downto 0)
             );
     end component;
-    constant interval : time := 10 ns;
+    constant interval : time := 15 ns;
     constant dsize1 : integer := 1;
     constant dsize8 : integer := 8;
     constant dsize16 : integer := 16;
@@ -30,68 +30,68 @@ begin
     dut1 : regn generic map (dsize8) port map (cclk, een, rr8, qq8);
     dut2 : regn generic map (dsize16) port map (cclk, een, rr16, qq16);
 
-    p : process
+    p1 : process
     variable i : integer := 0;
-    constant loopcnt : integer := 5;
+    constant loopcnt : integer := 10;
     begin
 
---        bb <= x"70";
---        mm <= "01100101";
---        ccin <= '0';
---        wait for interval;
---        assert (oo = x"e4" and ccout = '0' and vv = '1' ) 
---            report "adc error." severity warning;
---        if (cclk = '0') then
---            cclk <= '1';
---        else
---            cclk <= '0';
---        end if;
-        for i in 0 to loopcnt loop
+        for i in 0 to loopcnt * 2 loop
             cclk <= '1';
             wait for interval / 2;
             cclk <= '0';
             wait for interval / 2;
+        end loop;
+    end process;
+
+    p2 : process
+    variable i : integer := 0;
+    constant loopcnt : integer := 5;
+    begin
+
+        wait for interval / 4;
 
+        for i in 0 to loopcnt loop
             rr1 <= conv_std_logic_vector(i, dsize1);
             rr8 <= conv_std_logic_vector(i, dsize8);
             rr16 <= conv_std_logic_vector(i, dsize16);
+            wait for interval / 4;
         end loop;
 
         een <= '1';
 
-        for i in 0 to loopcnt loop
-            cclk <= '1';
-            wait for interval / 2;
-            cclk <= '0';
-            wait for interval / 2;
-
+        for i in 0 to loopcnt * 3 loop
             rr1 <= conv_std_logic_vector(i, dsize1);
             rr8 <= conv_std_logic_vector(i, dsize8);
             rr16 <= conv_std_logic_vector(i, dsize16);
+            wait for interval / 3;
         end loop;
 
-        for i in 0 to loopcnt loop
-            cclk <= '1';
-            wait for interval / 2;
-
-            cclk <= '0';
+        for i in 0 to loopcnt * 4 loop
             rr1 <= conv_std_logic_vector(i, dsize1);
             rr8 <= conv_std_logic_vector(i, dsize8);
             rr16 <= conv_std_logic_vector(i, dsize16);
-            wait for interval / 2;
+            wait for interval / 4;
         end loop;
 
-        een <= '0';
-
-        for i in 0 to loopcnt loop
-            cclk <= '1';
-            wait for interval / 2;
-            cclk <= '0';
-            wait for interval / 2;
+        for i in 0 to loopcnt * 5 loop
+            rr1 <= conv_std_logic_vector(i, dsize1);
+            rr8 <= conv_std_logic_vector(i, dsize8);
+            rr16 <= conv_std_logic_vector(i, dsize16);
+            wait for interval / 5;
+        end loop;
 
+        for i in 0 to loopcnt * 2 loop
+            rr1 <= conv_std_logic_vector(i, dsize1);
+            rr8 <= conv_std_logic_vector(i, dsize8);
+            rr16 <= conv_std_logic_vector(i, dsize16);
+            wait for interval;
+        end loop;
+        
+        for i in 0 to loopcnt * 2 loop
             rr1 <= conv_std_logic_vector(i, dsize1);
             rr8 <= conv_std_logic_vector(i, dsize8);
             rr16 <= conv_std_logic_vector(i, dsize16);
+            wait for interval * 2;
         end loop;
 
         wait;