V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <
20230215020539.4788-9-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
- if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
+ if (cpu->cfg.ext_zve32f) {
/*
* If env->vl equals to VLMAX, we can use generic vector operation
* expanders (GVEC) to accerlate the vector operations.
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
- if (env->misa_ext & RVV ||
- cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
+ if (cpu->cfg.ext_zve32f) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
{
TCGv s1, dst;
- if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
- s->cfg_ptr->ext_zve64f)) {
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
return false;
}
{
TCGv dst;
- if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
- s->cfg_ptr->ext_zve64f)) {
+ if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
return false;
}