BackMerge v4.18-rc7 into drm-next

rmk requested this for armada and I think we've had a few
conflicts build up.

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
Simple merge

diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 9f0a217,5a2e952..5167953
--- 1/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
--- 2/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@@ -74,4 -80,327 +74,3 @@@ bool dm_read_persistent_data(struct dc_
  
  /**** power component interfaces ****/
  
 -bool dm_pp_apply_display_requirements(
 -              const struct dc_context *ctx,
 -              const struct dm_pp_display_configuration *pp_display_cfg)
 -{
 -      struct amdgpu_device *adev = ctx->driver_context;
 -
 -      if (adev->pm.dpm_enabled) {
 -
 -              memset(&adev->pm.pm_display_cfg, 0,
 -                              sizeof(adev->pm.pm_display_cfg));
 -
 -              adev->pm.pm_display_cfg.cpu_cc6_disable =
 -                      pp_display_cfg->cpu_cc6_disable;
 -
 -              adev->pm.pm_display_cfg.cpu_pstate_disable =
 -                      pp_display_cfg->cpu_pstate_disable;
 -
 -              adev->pm.pm_display_cfg.cpu_pstate_separation_time =
 -                      pp_display_cfg->cpu_pstate_separation_time;
 -
 -              adev->pm.pm_display_cfg.nb_pstate_switch_disable =
 -                      pp_display_cfg->nb_pstate_switch_disable;
 -
 -              adev->pm.pm_display_cfg.num_display =
 -                              pp_display_cfg->display_count;
 -              adev->pm.pm_display_cfg.num_path_including_non_display =
 -                              pp_display_cfg->display_count;
 -
 -              adev->pm.pm_display_cfg.min_core_set_clock =
 -                              pp_display_cfg->min_engine_clock_khz/10;
 -              adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
 -                              pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
 -              adev->pm.pm_display_cfg.min_mem_set_clock =
 -                              pp_display_cfg->min_memory_clock_khz/10;
 -
 -              adev->pm.pm_display_cfg.multi_monitor_in_sync =
 -                              pp_display_cfg->all_displays_in_sync;
 -              adev->pm.pm_display_cfg.min_vblank_time =
 -                              pp_display_cfg->avail_mclk_switch_time_us;
 -
 -              adev->pm.pm_display_cfg.display_clk =
 -                              pp_display_cfg->disp_clk_khz/10;
 -
 -              adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
 -                              pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
 -
 -              adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
 -              adev->pm.pm_display_cfg.line_time_in_us =
 -                              pp_display_cfg->line_time_in_us;
 -
 -              adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
 -              adev->pm.pm_display_cfg.crossfire_display_index = -1;
 -              adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
 -
 -              /* TODO: complete implementation of
 -               * pp_display_configuration_change().
 -               * Follow example of:
 -               * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
 -               * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
 -              if (adev->powerplay.pp_funcs->display_configuration_change)
 -                      adev->powerplay.pp_funcs->display_configuration_change(
 -                              adev->powerplay.pp_handle,
 -                              &adev->pm.pm_display_cfg);
 -
 -              /* TODO: replace by a separate call to 'apply display cfg'? */
 -              amdgpu_pm_compute_clocks(adev);
 -      }
 -
 -      return true;
 -}
 -
 -static void get_default_clock_levels(
 -              enum dm_pp_clock_type clk_type,
 -              struct dm_pp_clock_levels *clks)
 -{
 -      uint32_t disp_clks_in_khz[6] = {
 -                      300000, 400000, 496560, 626090, 685720, 757900 };
 -      uint32_t sclks_in_khz[6] = {
 -                      300000, 360000, 423530, 514290, 626090, 720000 };
 -      uint32_t mclks_in_khz[2] = { 333000, 800000 };
 -
 -      switch (clk_type) {
 -      case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
 -              clks->num_levels = 6;
 -              memmove(clks->clocks_in_khz, disp_clks_in_khz,
 -                              sizeof(disp_clks_in_khz));
 -              break;
 -      case DM_PP_CLOCK_TYPE_ENGINE_CLK:
 -              clks->num_levels = 6;
 -              memmove(clks->clocks_in_khz, sclks_in_khz,
 -                              sizeof(sclks_in_khz));
 -              break;
 -      case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 -              clks->num_levels = 2;
 -              memmove(clks->clocks_in_khz, mclks_in_khz,
 -                              sizeof(mclks_in_khz));
 -              break;
 -      default:
 -              clks->num_levels = 0;
 -              break;
 -      }
 -}
 -
 -static enum amd_pp_clock_type dc_to_pp_clock_type(
 -              enum dm_pp_clock_type dm_pp_clk_type)
 -{
 -      enum amd_pp_clock_type amd_pp_clk_type = 0;
 -
 -      switch (dm_pp_clk_type) {
 -      case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
 -              amd_pp_clk_type = amd_pp_disp_clock;
 -              break;
 -      case DM_PP_CLOCK_TYPE_ENGINE_CLK:
 -              amd_pp_clk_type = amd_pp_sys_clock;
 -              break;
 -      case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 -              amd_pp_clk_type = amd_pp_mem_clock;
 -              break;
 -      default:
 -              DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
 -                              dm_pp_clk_type);
 -              break;
 -      }
 -
 -      return amd_pp_clk_type;
 -}
 -
 -static void pp_to_dc_clock_levels(
 -              const struct amd_pp_clocks *pp_clks,
 -              struct dm_pp_clock_levels *dc_clks,
 -              enum dm_pp_clock_type dc_clk_type)
 -{
 -      uint32_t i;
 -
 -      if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
 -              DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
 -                              DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
 -                              pp_clks->count,
 -                              DM_PP_MAX_CLOCK_LEVELS);
 -
 -              dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
 -      } else
 -              dc_clks->num_levels = pp_clks->count;
 -
 -      DRM_INFO("DM_PPLIB: values for %s clock\n",
 -                      DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 -
 -      for (i = 0; i < dc_clks->num_levels; i++) {
 -              DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
 -              /* translate 10kHz to kHz */
 -              dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
 -      }
 -}
 -
 -static void pp_to_dc_clock_levels_with_latency(
 -              const struct pp_clock_levels_with_latency *pp_clks,
 -              struct dm_pp_clock_levels_with_latency *clk_level_info,
 -              enum dm_pp_clock_type dc_clk_type)
 -{
 -      uint32_t i;
 -
 -      if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
 -              DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
 -                              DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
 -                              pp_clks->num_levels,
 -                              DM_PP_MAX_CLOCK_LEVELS);
 -
 -              clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
 -      } else
 -              clk_level_info->num_levels = pp_clks->num_levels;
 -
 -      DRM_DEBUG("DM_PPLIB: values for %s clock\n",
 -                      DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 -
 -      for (i = 0; i < clk_level_info->num_levels; i++) {
 -              DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
 -              /* translate 10kHz to kHz */
 -              clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
 -              clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
 -      }
 -}
 -
 -bool dm_pp_get_clock_levels_by_type(
 -              const struct dc_context *ctx,
 -              enum dm_pp_clock_type clk_type,
 -              struct dm_pp_clock_levels *dc_clks)
 -{
 -      struct amdgpu_device *adev = ctx->driver_context;
 -      void *pp_handle = adev->powerplay.pp_handle;
 -      struct amd_pp_clocks pp_clks = { 0 };
 -      struct amd_pp_simple_clock_info validation_clks = { 0 };
 -      uint32_t i;
 -
 -      if (adev->powerplay.pp_funcs->get_clock_by_type) {
 -              if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
 -                      dc_to_pp_clock_type(clk_type), &pp_clks)) {
 -              /* Error in pplib. Provide default values. */
 -                      get_default_clock_levels(clk_type, dc_clks);
 -                      return true;
 -              }
 -      }
 -
 -      pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
 -
 -      if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
 -              if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
 -                                              pp_handle, &validation_clks)) {
 -                      /* Error in pplib. Provide default values. */
 -                      DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
 -                      validation_clks.engine_max_clock = 72000;
 -                      validation_clks.memory_max_clock = 80000;
 -                      validation_clks.level = 0;
 -              }
 -      }
 -
 -      DRM_INFO("DM_PPLIB: Validation clocks:\n");
 -      DRM_INFO("DM_PPLIB:    engine_max_clock: %d\n",
 -                      validation_clks.engine_max_clock);
 -      DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
 -                      validation_clks.memory_max_clock);
 -      DRM_INFO("DM_PPLIB:    level           : %d\n",
 -                      validation_clks.level);
 -
 -      /* Translate 10 kHz to kHz. */
 -      validation_clks.engine_max_clock *= 10;
 -      validation_clks.memory_max_clock *= 10;
 -
 -      /* Determine the highest non-boosted level from the Validation Clocks */
 -      if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
 -              for (i = 0; i < dc_clks->num_levels; i++) {
 -                      if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
 -                              /* This clock is higher the validation clock.
 -                               * Than means the previous one is the highest
 -                               * non-boosted one. */
 -                              DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
 -                                              dc_clks->num_levels, i);
 -                              dc_clks->num_levels = i > 0 ? i : 1;
 -                              break;
 -                      }
 -              }
 -      } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
 -              for (i = 0; i < dc_clks->num_levels; i++) {
 -                      if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
 -                              DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
 -                                              dc_clks->num_levels, i);
 -                              dc_clks->num_levels = i > 0 ? i : 1;
 -                              break;
 -                      }
 -              }
 -      }
 -
 -      return true;
 -}
 -
 -bool dm_pp_get_clock_levels_by_type_with_latency(
 -      const struct dc_context *ctx,
 -      enum dm_pp_clock_type clk_type,
 -      struct dm_pp_clock_levels_with_latency *clk_level_info)
 -{
 -      struct amdgpu_device *adev = ctx->driver_context;
 -      void *pp_handle = adev->powerplay.pp_handle;
 -      struct pp_clock_levels_with_latency pp_clks = { 0 };
 -      const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 -
 -      if (!pp_funcs || !pp_funcs->get_clock_by_type_with_latency)
 -              return false;
 -
 -      if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
 -                                                   dc_to_pp_clock_type(clk_type),
 -                                                   &pp_clks))
 -              return false;
 -
 -      pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
 -
 -      return true;
 -}
 -
 -bool dm_pp_get_clock_levels_by_type_with_voltage(
 -      const struct dc_context *ctx,
 -      enum dm_pp_clock_type clk_type,
 -      struct dm_pp_clock_levels_with_voltage *clk_level_info)
 -{
 -      /* TODO: to be implemented */
 -      return false;
 -}
 -
 -bool dm_pp_notify_wm_clock_changes(
 -      const struct dc_context *ctx,
 -      struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
 -{
 -      /* TODO: to be implemented */
 -      return false;
 -}
 -
 -bool dm_pp_apply_power_level_change_request(
 -      const struct dc_context *ctx,
 -      struct dm_pp_power_level_change_request *level_change_req)
 -{
 -      /* TODO: to be implemented */
 -      return false;
 -}
 -
 -bool dm_pp_apply_clock_for_voltage_request(
 -      const struct dc_context *ctx,
 -      struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
 -{
 -      /* TODO: to be implemented */
 -      return false;
 -}
 -
 -bool dm_pp_get_static_clocks(
 -      const struct dc_context *ctx,
 -      struct dm_pp_static_clock_info *static_clk_info)
 -{
 -      /* TODO: to be implemented */
 -      return false;
 -}
 -
 -void dm_pp_get_funcs_rv(
 -              struct dc_context *ctx,
 -              struct pp_smu_funcs_rv *funcs)
 -{}
--
 -/**** end of power component interfaces ****/

diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
Simple merge

diff --cc drivers/gpu/drm/amd/display/dc/dc.h
Simple merge

diff --cc drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
Simple merge

diff --cc drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
index f4f366b,2991470..cb3a5b1
--- 1/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
--- 2/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
@@@ -224,8 -224,14 +224,10 @@@ static int append_vbios_pptable(struct 
        ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent;
        ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq;
  
 -      /* 0xFFFF will disable the ACG feature */
 -      if (!(hwmgr->feature_mask & PP_ACG_MASK)) {
 -              ppsmc_pptable->AcgThresholdFreqHigh = 0xFFFF;
 -              ppsmc_pptable->AcgThresholdFreqLow = 0xFFFF;
 -      }
 +      ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
  
+       ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
+ 
        return 0;
  }
  

diff --cc drivers/gpu/drm/etnaviv/etnaviv_drv.c
Simple merge

diff --cc drivers/gpu/drm/etnaviv/etnaviv_sched.c
Simple merge

diff --cc drivers/gpu/drm/i915/gvt/cmd_parser.c
Simple merge

diff --cc drivers/gpu/drm/i915/gvt/display.c
Simple merge

diff --cc drivers/gpu/drm/i915/gvt/gtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gvt/gtt.h
Simple merge

diff --cc drivers/gpu/drm/i915/gvt/gvt.h
Simple merge

diff --cc drivers/gpu/drm/i915/gvt/handlers.c
Simple merge

diff --cc drivers/gpu/drm/i915/gvt/mmio.h
Simple merge

diff --cc drivers/gpu/drm/i915/gvt/mmio_context.c
Simple merge

diff --cc drivers/gpu/drm/nouveau/dispnv50/disp.c
Simple merge

diff --cc drivers/gpu/drm/nouveau/nouveau_connector.c
Simple merge

diff --cc drivers/gpu/drm/nouveau/nouveau_display.c
Simple merge

diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
Simple merge

diff --cc drivers/gpu/drm/nouveau/nouveau_gem.c
Simple merge

diff --cc drivers/gpu/drm/sun4i/Makefile
Simple merge

diff --cc drivers/pci/pci.c
Simple merge

diff --cc include/linux/pci.h
Simple merge