RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the
cpu->cfg.pmp flag. Use the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <
20230222185205.355361-8-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
riscv_set_feature(env, RISCV_FEATURE_MMU);
}
- if (cpu->cfg.pmp) {
- riscv_set_feature(env, RISCV_FEATURE_PMP);
- }
-
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
so a cpu features bitfield is required, likewise for optional PMP support */
enum {
RISCV_FEATURE_MMU,
- RISCV_FEATURE_PMP,
};
/* Privileged specification version */
pmp_priv_t pmp_priv;
int pmp_index = -1;
- if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+ if (!riscv_cpu_cfg(env)->pmp) {
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
}
static RISCVException pmp(CPURISCVState *env, int csrno)
{
- if (riscv_feature(env, RISCV_FEATURE_PMP)) {
+ if (riscv_cpu_cfg(env)->pmp) {
return RISCV_EXCP_NONE;
}
static bool pmp_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
- CPURISCVState *env = &cpu->env;
- return riscv_feature(env, RISCV_FEATURE_PMP);
+ return cpu->cfg.pmp;
}
static int pmp_post_load(void *opaque, int version_id)
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
- if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+ if (riscv_cpu_cfg(env)->pmp &&
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
}
}
}
- if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+ if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) {
/*
* Privileged spec v1.10 states if HW doesn't implement any PMP entry
* or no PMP entry matches an M-Mode access, the access succeeds.