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e1000e: cleanup - move defines to appropriate header file
authorBruce Allan <bruce.w.allan@intel.com>
Wed, 20 Feb 2013 04:06:43 +0000 (04:06 +0000)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Fri, 8 Mar 2013 09:53:29 +0000 (01:53 -0800)
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/e1000e/82571.h
drivers/net/ethernet/intel/e1000e/defines.h
drivers/net/ethernet/intel/e1000e/ethtool.c
drivers/net/ethernet/intel/e1000e/netdev.c

index 85cb1a3..08e24dc 100644 (file)
@@ -44,6 +44,8 @@
 #define E1000_EIAC_82574       0x000DC /* Ext. Interrupt Auto Clear - RW */
 #define E1000_EIAC_MASK_82574  0x01F00000
 
+#define E1000_IVAR_INT_ALLOC_VALID     0x8
+
 /* Manageability Operation Mode mask */
 #define E1000_NVM_INIT_CTRL2_MNGM      0x6000
 
index e6fe090..b7c664f 100644 (file)
 #define E1000_CTRL_MEHE     0x00080000  /* Memory Error Handling Enable */
 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
+#define E1000_CTRL_ADVD3WUC 0x00100000  /* D3 WUC */
+#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
 #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
 #define E1000_CTRL_RST      0x04000000  /* Global reset */
 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 
 /* SerDes Control */
 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
+#define E1000_SCTL_ENABLE_SERDES_LOOPBACK      0x0410
 
 /* Receive Checksum Control */
 #define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
index 23d5d90..8f5832c 100644 (file)
@@ -1432,8 +1432,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
        /* special write to serdes control register to enable SerDes analog
         * loopback
         */
-#define E1000_SERDES_LB_ON 0x410
-       ew32(SCTL, E1000_SERDES_LB_ON);
+       ew32(SCTL, E1000_SCTL_ENABLE_SERDES_LOOPBACK);
        e1e_flush();
        usleep_range(10000, 20000);
 
@@ -1527,8 +1526,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
        case e1000_82572:
                if (hw->phy.media_type == e1000_media_type_fiber ||
                    hw->phy.media_type == e1000_media_type_internal_serdes) {
-#define E1000_SERDES_LB_OFF 0x400
-                       ew32(SCTL, E1000_SERDES_LB_OFF);
+                       ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
                        e1e_flush();
                        usleep_range(10000, 20000);
                        break;
index b085ce1..b4eab18 100644 (file)
@@ -1957,7 +1957,6 @@ static void e1000_configure_msix(struct e1000_adapter *adapter)
                ew32(RFCTL, rfctl);
        }
 
-#define E1000_IVAR_INT_ALLOC_VALID     0x8
        /* Configure Rx vector */
        rx_ring->ims_val = E1000_IMS_RXQ0;
        adapter->eiac_mask |= rx_ring->ims_val;
@@ -5911,10 +5910,6 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
                }
 
                ctrl = er32(CTRL);
-               /* advertise wake from D3Cold */
-               #define E1000_CTRL_ADVD3WUC 0x00100000
-               /* phy power management enable */
-               #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
                ctrl |= E1000_CTRL_ADVD3WUC;
                if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
                        ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;