drm/amd/pm: add callback get_dpm_ultimate_freq for yellow carp

Add callback function to get the hard frequency range of a clock domain
for yellow carp.

Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index bded5c2..080dd76 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -670,6 +670,116 @@ static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
        return smu_cmn_feature_is_enabled(smu, feature_id);
 }
 
+static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
+                                                       enum smu_clk_type clk_type,
+                                                       uint32_t *min,
+                                                       uint32_t *max)
+{
+       DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+       uint32_t clock_limit;
+       uint32_t max_dpm_level, min_dpm_level;
+       int ret = 0;
+
+       if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
+               switch (clk_type) {
+               case SMU_MCLK:
+               case SMU_UCLK:
+                       clock_limit = smu->smu_table.boot_values.uclk;
+                       break;
+               case SMU_FCLK:
+                       clock_limit = smu->smu_table.boot_values.fclk;
+                       break;
+               case SMU_GFXCLK:
+               case SMU_SCLK:
+                       clock_limit = smu->smu_table.boot_values.gfxclk;
+                       break;
+               case SMU_SOCCLK:
+                       clock_limit = smu->smu_table.boot_values.socclk;
+                       break;
+               case SMU_VCLK:
+                       clock_limit = smu->smu_table.boot_values.vclk;
+                       break;
+               case SMU_DCLK:
+                       clock_limit = smu->smu_table.boot_values.dclk;
+                       break;
+               default:
+                       clock_limit = 0;
+                       break;
+               }
+
+               /* clock in Mhz unit */
+               if (min)
+                       *min = clock_limit / 100;
+               if (max)
+                       *max = clock_limit / 100;
+
+               return 0;
+       }
+
+       if (max) {
+               switch (clk_type) {
+               case SMU_GFXCLK:
+               case SMU_SCLK:
+                       *max = clk_table->MaxGfxClk;
+                       break;
+               case SMU_MCLK:
+               case SMU_UCLK:
+               case SMU_FCLK:
+                       max_dpm_level = 0;
+                       break;
+               case SMU_SOCCLK:
+                       max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
+                       break;
+               case SMU_VCLK:
+               case SMU_DCLK:
+                       max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
+                       break;
+               default:
+                       ret = -EINVAL;
+                       goto failed;
+               }
+
+               if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
+                       ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
+                       if (ret)
+                               goto failed;
+               }
+       }
+
+       if (min) {
+               switch (clk_type) {
+               case SMU_GFXCLK:
+               case SMU_SCLK:
+                       *min = clk_table->MinGfxClk;
+                       break;
+               case SMU_MCLK:
+               case SMU_UCLK:
+               case SMU_FCLK:
+                       min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
+                       break;
+               case SMU_SOCCLK:
+                       min_dpm_level = 0;
+                       break;
+               case SMU_VCLK:
+               case SMU_DCLK:
+                       min_dpm_level = 0;
+                       break;
+               default:
+                       ret = -EINVAL;
+                       goto failed;
+               }
+
+               if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
+                       ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
+                       if (ret)
+                               goto failed;
+               }
+       }
+
+failed:
+       return ret;
+}
+
 static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
                                                        enum smu_clk_type clk_type,
                                                        uint32_t min,
@@ -835,6 +945,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = {
        .set_driver_table_location = smu_v13_0_1_set_driver_table_location,
        .gfx_off_control = smu_v13_0_1_gfx_off_control,
        .post_init = yellow_carp_post_smu_init,
+       .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
        .od_edit_dpm_table = yellow_carp_od_edit_dpm_table,
        .print_clk_levels = yellow_carp_print_clk_levels,
        .force_clk_levels = yellow_carp_force_clk_levels,