- lsr acc ok

- pha ok
- adc zp ok.

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index f85047d..40a0008 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -199,10 +199,10 @@ constant ALU_BIT    : std_logic_vector (3 downto 0) := "0011";
 constant ALU_ADC    : std_logic_vector (3 downto 0) := "0100";
 constant ALU_SBC    : std_logic_vector (3 downto 0) := "0101";
 constant ALU_CMP    : std_logic_vector (3 downto 0) := "0110";
-constant ALU_SL     : std_logic_vector (3 downto 0) := "0111";
-constant ALU_SR     : std_logic_vector (3 downto 0) := "1000";
-constant ALU_RL     : std_logic_vector (3 downto 0) := "1001";
-constant ALU_RR     : std_logic_vector (3 downto 0) := "1010";
+constant ALU_ASL    : std_logic_vector (3 downto 0) := "0111";
+constant ALU_LSR    : std_logic_vector (3 downto 0) := "1000";
+constant ALU_ROL    : std_logic_vector (3 downto 0) := "1001";
+constant ALU_ROR    : std_logic_vector (3 downto 0) := "1010";
 constant ALU_INC    : std_logic_vector (3 downto 0) := "1011";
 constant ALU_DEC    : std_logic_vector (3 downto 0) := "1100";
 
@@ -494,6 +494,14 @@ end procedure;
             set_nz;
             output_d_bus;
 
+        elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
+            --lsr acc.
+            sel <= ALU_LSR;
+            d1 <= acc_out;
+            set_nz;
+            carry_out <= c;
+            output_d_bus;
+
         --instruction is aaabbbcc format.
         elsif instruction (1 downto 0) = "01" then
             if instruction (7 downto 5) = "000" then
@@ -506,7 +514,7 @@ end procedure;
                 set_nz;
 
             elsif instruction (7 downto 5) = "001" then
-                d_print("and");
+                --d_print("and");
                 sel <= ALU_AND;
                 d1 <= acc_out;
                 d2 <= int_d_bus;
@@ -518,7 +526,7 @@ end procedure;
                 d_print("eor");
 
             elsif instruction (7 downto 5) = "011" then
-                d_print("adc");
+                --d_print("adc");
                 sel <= ALU_ADC;
                 d1 <= acc_out;
                 d2 <= int_d_bus;
@@ -745,10 +753,10 @@ constant ALU_BIT    : std_logic_vector (3 downto 0) := "0011";
 constant ALU_ADC    : std_logic_vector (3 downto 0) := "0100";
 constant ALU_SBC    : std_logic_vector (3 downto 0) := "0101";
 constant ALU_CMP    : std_logic_vector (3 downto 0) := "0110";
-constant ALU_SL     : std_logic_vector (3 downto 0) := "0111";
-constant ALU_SR     : std_logic_vector (3 downto 0) := "1000";
-constant ALU_RL     : std_logic_vector (3 downto 0) := "1001";
-constant ALU_RR     : std_logic_vector (3 downto 0) := "1010";
+constant ALU_ASL    : std_logic_vector (3 downto 0) := "0111";
+constant ALU_LSR    : std_logic_vector (3 downto 0) := "1000";
+constant ALU_ROL    : std_logic_vector (3 downto 0) := "1001";
+constant ALU_ROR    : std_logic_vector (3 downto 0) := "1010";
 constant ALU_INC    : std_logic_vector (3 downto 0) := "1011";
 constant ALU_DEC    : std_logic_vector (3 downto 0) := "1100";
 
@@ -824,13 +832,21 @@ end procedure;
         set_n(res(dsize - 1 downto 0));
         set_z(res(dsize - 1 downto 0));
 
-    elsif sel = ALU_SL then
+    elsif sel = ALU_ASL then
         ----
-    elsif sel = ALU_SR then
-        ----
-    elsif sel = ALU_RL then
+    elsif sel = ALU_LSR then
+        res(dsize - 2 downto 0) := d1(dsize - 1 downto 1);
+        res(dsize - 1) := '0';
+        res(dsize) := d1(0);
+
+        d_out <= res(dsize - 1 downto 0);
+        set_n(res(dsize - 1 downto 0));
+        set_z(res(dsize - 1 downto 0));
+        carry_out <= res(dsize);
+
+    elsif sel = ALU_ROL then
         ----
-    elsif sel = ALU_RR then
+    elsif sel = ALU_ROR then
         ----
     elsif sel = ALU_INC then
         res := ('0' & d1) + "000000001";

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 38e6f35..7e46fd8 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -285,6 +285,14 @@ begin
     stat_bus_nz_n <= '0';
 end  procedure;
 
+procedure set_nzc_from_bus is
+begin
+    --status register n,z,c bit update.
+    stat_dec_oe_n <= '1';
+    status_reg <= "10000011";
+    stat_bus_nz_n <= '0';
+end  procedure;
+
 procedure set_nz_from_alu is
 begin
     --status register n/z/c bit update.
@@ -635,6 +643,23 @@ begin
 end  procedure;
 
 
+-- A.5.1 push stack
+procedure a51_push is
+begin
+    if exec_cycle = T1 then
+        fetch_stop;
+        next_cycle <= T2;
+    elsif exec_cycle = T2 then
+        back_oe(sp_cmd, '0');
+        back_we(sp_cmd, '0');
+        sp_push_n <= '0';
+        sp_oe_n <= '0';
+        r_nw <= '0';
+        next_cycle <= T0;
+    end if;
+end procedure;
+
+
 -- A.5.8 branch operations
 
 procedure a58_branch (int_flg : in integer; br_cond : in std_logic) is
@@ -804,6 +829,11 @@ end  procedure;
                 elsif instruction = conv_std_logic_vector(16#4a#, dsize) then
                     --lsr acc mode
                     d_print("lsr");
+                    arith_en_n <= '0';
+                    back_oe(acc_cmd, '0');
+                    front_we(acc_cmd, '0');
+                    set_nzc_from_bus;
+                    single_inst;
 
                 elsif instruction = conv_std_logic_vector(16#ea#, dsize) then
                     d_print("nop");
@@ -880,6 +910,13 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#65#, dsize) then
                     --zp
                     d_print("adc");
+                    a2_zp;
+                    if exec_cycle = T2 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        back_we(acc_cmd, '0');
+                        set_nvzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#75#, dsize) then
                     --zp, x
@@ -917,6 +954,13 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#25#, dsize) then
                     --zp
                     d_print("and");
+                    a2_zp;
+                    if exec_cycle = T2 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        back_we(acc_cmd, '0');
+                        set_nz_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#35#, dsize) then
                     --zp, x
@@ -1467,6 +1511,10 @@ end  procedure;
 
                 elsif instruction = conv_std_logic_vector(16#48#, dsize) then
                     d_print("pha");
+                    a51_push;
+                    if exec_cycle = T2 then
+                        front_oe(acc_cmd, '0');
+                    end if;
 
                 elsif instruction = conv_std_logic_vector(16#28#, dsize) then
                     d_print("plp");