bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
- // FIXME: temporary function to expose previous interface to call lowering
- // until it is refactored.
- /// Combines all component registers of \p V into a single scalar with size
- /// "max(Offsets) + last size".
- Register packRegs(const Value &V, MachineIRBuilder &MIRBuilder);
-
- void unpackRegs(const Value &V, Register Src, MachineIRBuilder &MIRBuilder);
-
/// Returns true if the value should be split into multiple LLTs.
/// If \p Offsets is given then the split type's offsets will be stored in it.
/// If \p Offsets is not empty it will be cleared first.
return true;
}
-Register IRTranslator::packRegs(const Value &V,
- MachineIRBuilder &MIRBuilder) {
- ArrayRef<Register> Regs = getOrCreateVRegs(V);
- ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
- LLT BigTy = getLLTForType(*V.getType(), *DL);
-
- if (Regs.size() == 1)
- return Regs[0];
-
- Register Dst = MRI->createGenericVirtualRegister(BigTy);
- MIRBuilder.buildUndef(Dst);
- for (unsigned i = 0; i < Regs.size(); ++i) {
- Register NewDst = MRI->createGenericVirtualRegister(BigTy);
- MIRBuilder.buildInsert(NewDst, Dst, Regs[i], Offsets[i]);
- Dst = NewDst;
- }
- return Dst;
-}
-
-void IRTranslator::unpackRegs(const Value &V, Register Src,
- MachineIRBuilder &MIRBuilder) {
- ArrayRef<Register> Regs = getOrCreateVRegs(V);
- ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
-
- for (unsigned i = 0; i < Regs.size(); ++i)
- MIRBuilder.buildExtract(Regs[i], Src, Offsets[i]);
-}
-
bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
const CallInst &CI = cast<CallInst>(U);
auto TII = MF->getTarget().getIntrinsicInfo();
// Some intrinsics take metadata parameters. Reject them.
if (isa<MetadataAsValue>(Arg))
return false;
- MIB.addUse(packRegs(*Arg, MIRBuilder));
+ ArrayRef<Register> VRegs = getOrCreateVRegs(*Arg);
+ if (VRegs.size() > 1)
+ return false;
+ MIB.addUse(VRegs[0]);
}
// Add a MachineMemOperand if it is a target mem intrinsic.