MI->getOperand(0).getReg() == ARM::SP) {
O << '\t' << "push";
printPredicateOperand(MI, 2, O);
+ if (Opcode == ARM::t2STMDB_UPD)
+ O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
return;
MI->getOperand(0).getReg() == ARM::SP) {
O << '\t' << "pop";
printPredicateOperand(MI, 2, O);
+ if (Opcode == ARM::t2LDMIA_UPD)
+ O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
return;
; DARWIN: sub.w sp, sp, #805306368
; DARWIN: sub sp, #20
; LINUX: test3:
-; LINUX: push {r4, r7, r11, lr}
+; LINUX: push.w {r4, r7, r11, lr}
; LINUX: sub.w sp, sp, #805306368
; LINUX: sub sp, #16
%retval = alloca i32, align 4
# CHECK: pkhbt r2, r4, r6
0xc4 0xea 0x06 0x02
-# CHECK: pop {r2, r4, r6, r8, r10, r12}
+# CHECK: pop.w {r2, r4, r6, r8, r10, r12}
0xbd 0xe8 0x54 0x15
-# CHECK: push {r2, r4, r6, r8, r10, r12}
+# CHECK: push.w {r2, r4, r6, r8, r10, r12}
0x2d 0xe9 0x54 0x15
# CHECK: rsbs r0, r0, #0