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MIPS: asm: r4kcache: Build flushing code for instruction cache
author
Leonid Yegoshin
<Leonid.Yegoshin@imgtec.com>
Mon, 16 Dec 2013 11:24:13 +0000
(11:24 +0000)
committer
Ralf Baechle
<ralf@linux-mips.org>
Wed, 26 Mar 2014 22:09:18 +0000
(23:09 +0100)
Build code to invalidate an address range in the instruction cache
using the Hit Invalidate cache operation.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
arch/mips/include/asm/r4kcache.h
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diff --git
a/arch/mips/include/asm/r4kcache.h
b/arch/mips/include/asm/r4kcache.h
index
c84cadd
..
789792e
100644
(file)
--- a/
arch/mips/include/asm/r4kcache.h
+++ b/
arch/mips/include/asm/r4kcache.h
@@
-456,6
+456,7
@@
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
protected_, loongson2_)
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
/* blast_inv_dcache_range */
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )