KVM: x86: Open code necessary bits of kvm_lapic_set_base() at vCPU RESET

Stuff vcpu->arch.apic_base and apic->base_address directly during APIC
reset, as opposed to bouncing through kvm_set_apic_base() while fudging
the ENABLE bit during creation to avoid the other, unwanted side effects.

This is a step towards consolidating the APIC RESET logic across x86,
VMX, and SVM.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210713163324.627647-18-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 0fb282b..295a9d0 100644 (file)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2321,7 +2321,6 @@ EXPORT_SYMBOL_GPL(kvm_apic_update_apicv);
 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
 {
        struct kvm_lapic *apic = vcpu->arch.apic;
-       u64 msr_val;
        int i;
 
        if (!apic)
@@ -2331,10 +2330,13 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
        hrtimer_cancel(&apic->lapic_timer.timer);
 
        if (!init_event) {
-               msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
+               vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |
+                                      MSR_IA32_APICBASE_ENABLE;
                if (kvm_vcpu_is_reset_bsp(vcpu))
-                       msr_val |= MSR_IA32_APICBASE_BSP;
-               kvm_lapic_set_base(vcpu, msr_val);
+                       vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
+
+               apic->base_address = APIC_DEFAULT_PHYS_BASE;
+
                kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
        }
        kvm_apic_set_version(apic->vcpu);
@@ -2477,11 +2479,6 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
                lapic_timer_advance_dynamic = false;
        }
 
-       /*
-        * APIC is created enabled. This will prevent kvm_lapic_set_base from
-        * thinking that APIC state has changed.
-        */
-       vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
        static_branch_inc(&apic_sw_disabled.key); /* sw disabled at reset */
        kvm_iodevice_init(&apic->dev, &apic_mmio_ops);