nmi work started.

diff --git a/de0_cv_nes/de0_cv_nes.qsf b/de0_cv_nes/de0_cv_nes.qsf
index 778c1e2..6c8526f 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.qsf
+++ b/de0_cv_nes/de0_cv_nes.qsf
@@ -99,10 +99,10 @@ set_global_assignment -name VHDL_FILE mem/ram.vhd
 set_global_assignment -name VHDL_FILE chip_selector.vhd\r
 \r
 #ppu\r
-set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
-set_global_assignment -name VHDL_FILE ppu/render.vhd\r
-set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
-#set_global_assignment -name VHDL_FILE dummy-ppu.vhd\r
+#set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
+#set_global_assignment -name VHDL_FILE ppu/render.vhd\r
+#set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
+set_global_assignment -name VHDL_FILE dummy-ppu.vhd\r
 \r
 #cpu\r
 set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r

diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd
index cab1b44..fc179c1 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.vhd
+++ b/de0_cv_nes/de0_cv_nes.vhd
@@ -83,7 +83,8 @@ architecture rtl of de0_cv_nes is
                 pi_oe_n        : in std_logic;\r
                 pi_we_n        : in std_logic;\r
                 pi_cpu_addr    : in std_logic_vector (2 downto 0);
-                pio_cpu_d      : inout std_logic_vector (7 downto 0);
+                pio_cpu_d      : inout std_logic_vector (7 downto 0);\r
+                po_vblank_n    : out std_logic;\r
 
                 po_v_ce_n       : out std_logic;\r
                 po_v_rd_n       : out std_logic;\r
@@ -318,6 +319,7 @@ begin
             wr_we_n,\r
             wr_addr(2 downto 0), \r
             wr_d_io,\r
+            wr_nmi_n,\r
 \r
             wr_v_ce_n,\r
             wr_v_rd_n,\r
@@ -453,7 +455,6 @@ begin
 \r
     wr_rdy <= '1';\r
     wr_irq_n <= '1';\r
-    wr_nmi_n <= '1';\r
 \r
     po_dbg_cnt <= reg_dbg_cnt;\r
     deb_cnt_p : process (pi_rst_n, pi_base_clk)\r

diff --git a/de0_cv_nes/dummy-ppu.vhd b/de0_cv_nes/dummy-ppu.vhd
index 0f0993a..a63cbbc 100644 (file)
--- a/de0_cv_nes/dummy-ppu.vhd
+++ b/de0_cv_nes/dummy-ppu.vhd
@@ -12,6 +12,7 @@ entity ppu is
                 pi_we_n        : in std_logic;\r
                 pi_cpu_addr    : in std_logic_vector (2 downto 0);\r
                 pio_cpu_d      : inout std_logic_vector (7 downto 0);\r
+                po_vblank_n    : out std_logic;\r
 \r
                 po_v_ce_n       : out std_logic;\r
                 po_v_rd_n       : out std_logic;\r
@@ -42,6 +43,7 @@ end ppu;
 architecture rtl of ppu is\r
 begin\r
     pio_cpu_d      <= (others => 'Z');\r
+    --po_vblank_n    <= '1';\r
 \r
     po_v_ce_n       <= 'Z';\r
     po_v_rd_n       <= 'Z';\r
@@ -65,6 +67,26 @@ begin
     po_ppu_mask        <= (others => 'Z');\r
     po_ppu_scroll_x    <= (others => 'Z');\r
     po_ppu_scroll_y    <= (others => 'Z');\r
+\r
+    --- initiate nmi.\r
+    nmi_p: process\r
+    constant nmi_wait     : time := 880us;\r
+    constant vblank_time     : time := 60 us;\r
+    variable wait_cnt : integer := 0;\r
+    begin\r
+\r
+        if (wait_cnt = 0) then\r
+            po_vblank_n <= '1';\r
+            wait for nmi_wait;\r
+            wait_cnt := wait_cnt + 1;\r
+        else\r
+            po_vblank_n <= '0';\r
+            wait for vblank_time ;\r
+            po_vblank_n <= '1';\r
+            wait for vblank_time / 4;\r
+        end if;\r
+    end process;\r
+\r
 end rtl;\r
 \r
 \r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index f6e5912..5931987 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -28,6 +28,7 @@ vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -
 \r
 add wave -label dbg_cnt -radix hex  sim:/testbench_motones_sim/sim_board/po_dbg_cnt;\r
 add wave -label rst_n               sim:/testbench_motones_sim/sim_board/pi_rst_n;\r
+add wave -label wr_nmi_n            sim:/testbench_motones_sim/sim_board/wr_nmi_n;\r
 #add wave -label base_clk            sim:/testbench_motones_sim/sim_board/pi_base_clk;\r
 add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en;\r
 add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en(0);\r
@@ -49,7 +50,7 @@ add wave -label reg_y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/r
 add wave -label reg_sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_sp;\r
 \r
 add wave -divider internal_reg\r
-#add wave -label reg_main_cur_state  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_main_state;\r
+add wave -label reg_main_cur_state  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_main_state;\r
 #add wave -label reg_sub_cur_state   sim:/testbench_motones_sim/sim_board/cpu_inst/reg_sub_state;\r
 add wave -label reg_pc_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_pc_l;\r
 add wave -label reg_pc_h -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_pc_h;\r
@@ -64,7 +65,7 @@ view signals
 run 25 us\r
 wave zoom full\r
 \r
-run 4923 us\r
+run 880 us\r
 \r
 \r
 ##################################### PPU part.... ###########################################\r

diff --git a/tools/regression-test/regression.asm b/tools/regression-test/regression.asm
index be4b7d6..edea782 100644 (file)
--- a/tools/regression-test/regression.asm
+++ b/tools/regression-test/regression.asm
@@ -33,31 +33,31 @@
     jsr init_global\r
     jsr init_ppu\r
 \r
-    lda ad_start_msg\r
-    sta $00\r
-    lda ad_start_msg+1\r
-    sta $01\r
-    jsr print_ln\r
-;    jsr print_ln\r
-;    jsr print_ln\r
-;    jsr print_ln\r
-;    jsr print_ln\r
+;    lda ad_start_msg\r
+;    sta $00\r
+;    lda ad_start_msg+1\r
+;    sta $01\r
 ;    jsr print_ln\r
+;;    jsr print_ln\r
+;;    jsr print_ln\r
+;;    jsr print_ln\r
+;;    jsr print_ln\r
+;;    jsr print_ln\r
+;;\r
+;;    ;;test start...\r
+;    jsr addr_test\r
+;    jsr single_inst_test\r
+;    jsr a2_inst_test\r
+;    jsr a3_inst_test\r
+;    jsr a4_inst_test\r
+;    jsr a5_inst_test\r
+;    jsr status_test\r
+;    jsr ppu_test\r
 ;\r
-;    ;;test start...\r
-    jsr addr_test\r
-    jsr single_inst_test\r
-    jsr a2_inst_test\r
-    jsr a3_inst_test\r
-    jsr a4_inst_test\r
-    jsr a5_inst_test\r
-    jsr status_test\r
-    jsr ppu_test\r
-\r
-    jsr pg_border_test\r
-    jsr dma_test\r
-\r
-    jsr simple_dma_test\r
+;    jsr pg_border_test\r
+;    jsr dma_test\r
+;\r
+;    jsr simple_dma_test\r
 \r
 .endproc\r
 \r