if(((data & mask) != 0) && (dma_transfer_phase)) {
cdrom_debug_log(_T("CAUSED DMA INTERRUPT FROM DMAC"));
//clear_event(this, event_drq);
- do_dma_eot(true);
+ //do_dma_eot(true);
+ dma_transfer_phase = false;
+ //dma_transfer = false;
+ //status_seek = false;
+ clear_event(this, event_drq);
+ write_signals(&outputs_drq, 0x00000000);
+ set_dma_intr(true);
}
break;
case SIG_TOWNS_CDROM_DMAACK:
uint32_t TOWNS_CDROM::read_dma_io8(uint32_t addr)
{
// bool is_empty = databuffer->empty();
- if(dma_transfer_phase) {
+ //if(dma_transfer_phase) {
fetch_datareg_8();
// ToDo: Force register EOT JOB IF (read_length <= 0) && (databuffer->empty()).
- }
+ if((read_length <= 0) && (databuffer->empty())) {
+ status_read_done(false);
+ }
+ //}
return data_reg.b.l;
}
uint32_t TOWNS_CDROM::read_dma_io16(uint32_t addr)
{
// bool is_empty = databuffer->empty();
- if(dma_transfer_phase) {
+ //if(dma_transfer_phase) {
fetch_datareg_16();
// ToDo: Force register EOT JOB IF (read_length <= 0) && (databuffer->empty()).
- }
+ if((read_length <= 0) && (databuffer->empty())) {
+ status_read_done(false);
+ }
+ //}
return data_reg.w;
}
case EVENT_CDROM_READY_EOT: // CALL END-OF-TRANSFER FROM CDC.
event_delay_ready = -1;
mcu_ready = true;
-// if(stat_reply_intr) {
-// set_mcu_intr(true);
-// }
-// if(req_status) {
- mcu_intr = true;
- if(!(mcu_intr_mask) && (stat_reply_intr)) {
- write_mcuint_signals();
- }
-// }
-// set_mcu_intr(true);
-
+ if(stat_reply_intr) {
+ set_mcu_intr(true);
+ }
break;
case EVENT_CDROM_READY_CDDAREPLY: // READY TO ACCEPT A COMMAND FROM CDC.
event_delay_ready = -1;
event_eot = -1;
clear_event(this, event_time_out);
if(dma_transfer_phase) {
- do_dma_eot(false);
+ //dma_transfer_phase = false;
+ //do_dma_eot(false);
}
break;
default:
dma->set_context_tc1(scsi, SIG_SCSI_EOT, 0xffffffff);
dma->set_context_tc3(cdrom, SIG_TOWNS_CDROM_DMAINT, 0xffffffff);
- dma->set_context_ack1(scsi_host, SIG_SCSI_ACK, 0xffffffff);
+ //dma->set_context_ack1(scsi_host, SIG_SCSI_ACK, 0xffffffff);
dma->set_context_ack3(cdrom, SIG_TOWNS_CDROM_DMAACK, 0xffffffff);
-
- //dma->set_context_ube1(scsi_host, SIG_SCSI_16BIT_BUS, 0x02);
-
+ dma->set_context_ube1(scsi_host, SIG_SCSI_16BIT_BUS, 0x02);
dma->set_context_child_dma(extra_dma);
floppy->set_context_fdc(fdc);
b16 = selch = base = 0;
cmd = tmp = 0;
req = sreq = 0;
- mask = 0x0f;
-// mask = 0x00;
+// mask = 0x0f;
+ mask = 0x00;
running = false;
reset_all_tc();
}
break;
case 0x0e:
sreq = data;
- for(int _ch = 0; _ch < 4; _ch++) {
- if((sreq & (1 << _ch)) != 0) {
- //if((dma[_ch].mode & 0xc0) == 0x40) { // Single
- do_dma_per_channel(_ch);
- //}
- }
+ if(!(_SINGLE_MODE_DMA)) {
+ do_dma();
}
break;
case 0x0f:
mask = data;
+ #if 0
for(int _ch = 0; _ch < 4; _ch++) {
- if(((sreq | req) & (1 << _ch)) != 0) {
- if((mask & (1 << _ch)) == 0) {
- do_dma_per_channel(_ch);
+ uint8_t bit = (1 << _ch);
+ if(((req | sreq) & bit) && !(mask & bit)) {
+ do_dma_per_channel(_ch);
+ }
+ }
+ #else
+ {
+ uint8_t bit = 0x0f; // Ch. 0 - 3
+ if((mask & bit) != bit) {
+ if(((req | sreq) & bit) != 0x00) {
+ do_dma();
}
}
}
- set_ube(selch);
+ #endif
+ //set_ube(selch);
break;
}
}
if(!(req & bit)) {
req |= bit;
if(!(_SINGLE_MODE_DMA)) {
- if((mask & (1 << ch)) == 0) { // MASK register MASKS DRQ.20200918 K.O
- // Without #define SINGLE_MODE_DMA ,
- // DMA trasfer is triggerd by SIGNAL or writing I/O 0Eh.
- do_dma_per_channel(ch);
- req &= ~bit;
- }
+ do_dma();
}
}
} else {
c = c & 3;
uint8_t bit = 1 << c;
-#if 1 /* SYNC TO UPSTREAM */
+#if 0 /* SYNC TO UPSTREAM */
if(dma[c].creg-- == 0) {
//if(dma[c].endreq) dma[c].end = true;
if(dma[c].mode & 0x10) {
#else
// if(dma[c].end) return true; // OK?
if((dma[c].creg == 0) || ((dma[c].endreq) && !(dma[c].end) && ((dma[c].mode & 0xc0) != 0x40))) { // OK?
- //if(dma[c].endreq) dma[c].end = true;
+ if(dma[c].endreq) dma[c].end = true;
bool is_tc = false;
dma[c].creg--;
- //if(dma[c].end) is_tc = true;
+ if(dma[c].end) is_tc = true;
// TC
if(dma[c].bcreg < dma[c].creg) {
is_tc = true;
// -- 20200316 K.O
if((dma[c].mode & 0xc0) == 0x40){
// single mode
- //req &= ~bit;
- //sreq &= ~bit;
+ req &= ~bit;
+ sreq &= ~bit;
running = false;
return true;
+ } else if((dma[c].mode & 0xc0) == 0x00){
+ // demand mode
+ req &= ~bit;
+ sreq &= ~bit;
+ running = false;
+ return false;
}
#endif
return false;
if(cmd & 4) {
return true;
}
-// if(dma[c].end) {
-// if((dma[c].mode & 0xc0) != 0x40) { // Without Single
-// return true;
-// }
-// }
+ if(dma[c].end) {
+ if((dma[c].mode & 0xc0) != 0x40) { // Without Single
+ return true;
+ }
+ }
uint8_t bit = 1 << c;
if(((req | sreq) & bit) /*&& !(mask & bit)*/) {
}
do_dma_inc_dec_ptr_8bit(c);
}
- if(d_cpu != NULL) d_cpu->set_extra_clock(wait);
-
set_dma_ack(c);
+ if(d_cpu != NULL) d_cpu->set_extra_clock(wait);
if(do_dma_epilogue(c)) {
// //break;
// if(_SINGLE_MODE_DMA) {
// run dma
for(int c = 0; c < 4; c++) {
- if((mask & (1 << c)) == 0) { // MASK
+ uint8_t bit = 1 << c;
+ if(((req | sreq) & bit) && !(mask & bit)) {
+ //if((mask & (1 << c)) == 0) { // MASK
if((dma[c].mode & 0xc0) == 0x00) { // Demand
- //if(!(dma[c].end)) {
+ if(!(dma[c].end)) {
do_dma_per_channel(c);
- //}
+ }
} else if((dma[c].mode & 0xc0) == 0x40) { // Single
if(do_dma_per_channel(c)) break;
} else if((dma[c].mode & 0xc0) == 0xc0) { // Block (ToDo)