drm/i915: Add dev_priv->psr_mmio_base

Drop the EDP_PSR_BASE() thing, and just stick the PSR register offset
under dev_priv, like we for DSI and GPIO for example.

TODO: could probably move a bunch of this kind of stuff into the device
info instead...

v2: Drop the spurious whitespace change (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1447266856-30249-7-git-send-email-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e9ecabf..e38a89b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2561,7 +2561,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
                   yesno(work_busy(&dev_priv->psr.work.work)));
 
        if (HAS_DDI(dev))
-               enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+               enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
        else {
                for_each_pipe(dev_priv, pipe) {
                        stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
@@ -2583,7 +2583,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 
        /* CHV PSR has no kind of performance counter */
        if (HAS_DDI(dev)) {
-               psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
+               psrperf = I915_READ(EDP_PSR_PERF_CNT) &
                        EDP_PSR_PERF_CNT_MASK;
 
                seq_printf(m, "Performance_Counter: %u\n", psrperf);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 825e870..b9ed227 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1717,6 +1717,8 @@ struct drm_i915_private {
        /* MMIO base address for MIPI regs */
        uint32_t mipi_mmio_base;
 
+       uint32_t psr_mmio_base;
+
        wait_queue_head_t gmbus_wait_queue;
 
        struct pci_dev *bridge_dev;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 85d8878..341925c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3075,8 +3075,9 @@ enum skl_disp_power_wells {
 #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB)
 
 /* HSW+ eDP PSR registers */
-#define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
-#define EDP_PSR_CTL(dev)                       (EDP_PSR_BASE(dev) + 0)
+#define HSW_EDP_PSR_BASE       0x64800
+#define BDW_EDP_PSR_BASE       0x6f800
+#define EDP_PSR_CTL                            (dev_priv->psr_mmio_base + 0)
 #define   EDP_PSR_ENABLE                       (1<<31)
 #define   BDW_PSR_SINGLE_FRAME                 (1<<30)
 #define   EDP_PSR_LINK_STANDBY                 (1<<27)
@@ -3099,10 +3100,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_TP1_TIME_0us                 (3<<4)
 #define   EDP_PSR_IDLE_FRAME_SHIFT             0
 
-#define EDP_PSR_AUX_CTL(dev)                   (EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA(dev, i)               (EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
+#define EDP_PSR_AUX_CTL                                (dev_priv->psr_mmio_base + 0x10)
+#define EDP_PSR_AUX_DATA(i)                    (dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
 
-#define EDP_PSR_STATUS_CTL(dev)                        (EDP_PSR_BASE(dev) + 0x40)
+#define EDP_PSR_STATUS_CTL                     (dev_priv->psr_mmio_base + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK            (7<<29)
 #define   EDP_PSR_STATUS_STATE_IDLE            (0<<29)
 #define   EDP_PSR_STATUS_STATE_SRDONACK                (1<<29)
@@ -3126,10 +3127,10 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_STATUS_SENDING_TP1           (1<<4)
 #define   EDP_PSR_STATUS_IDLE_MASK             0xf
 
-#define EDP_PSR_PERF_CNT(dev)          (EDP_PSR_BASE(dev) + 0x44)
+#define EDP_PSR_PERF_CNT               (dev_priv->psr_mmio_base + 0x44)
 #define   EDP_PSR_PERF_CNT_MASK                0xffffff
 
-#define EDP_PSR_DEBUG_CTL(dev)         (EDP_PSR_BASE(dev) + 0x60)
+#define EDP_PSR_DEBUG_CTL              (dev_priv->psr_mmio_base + 0x60)
 #define   EDP_PSR_DEBUG_MASK_LPSP      (1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP     (1<<26)
 #define   EDP_PSR_DEBUG_MASK_HPD       (1<<25)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ff66718..3c973c5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -183,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                                DP_AUX_FRAME_SYNC_ENABLE);
 
        aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-               DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
+               DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(0);
        aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-               DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
+               DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL;
 
        /* Setup AUX registers */
        for (i = 0; i < sizeof(aux_msg); i += 4)
@@ -277,7 +277,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
                idle_frames += 4;
        }
 
-       I915_WRITE(EDP_PSR_CTL(dev), val |
+       I915_WRITE(EDP_PSR_CTL, val |
                   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
                   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
                   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
@@ -341,7 +341,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
 
-       WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+       WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
        WARN_ON(dev_priv->psr.active);
        lockdep_assert_held(&dev_priv->psr.lock);
 
@@ -405,7 +405,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
                }
 
                /* Avoid continuous PSR exit by masking memup and hpd */
-               I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
+               I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
                           EDP_PSR_DEBUG_MASK_HPD);
 
                /* Enable PSR on the panel */
@@ -467,17 +467,17 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
        struct drm_i915_private *dev_priv = dev->dev_private;
 
        if (dev_priv->psr.active) {
-               I915_WRITE(EDP_PSR_CTL(dev),
-                          I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
+               I915_WRITE(EDP_PSR_CTL,
+                          I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 
                /* Wait till PSR is idle */
-               if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
+               if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
                               EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
                        DRM_ERROR("Timed out waiting for PSR Idle State\n");
 
                dev_priv->psr.active = false;
        } else {
-               WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
+               WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
        }
 }
 
@@ -524,7 +524,7 @@ static void intel_psr_work(struct work_struct *work)
         * and be ready for re-enable.
         */
        if (HAS_DDI(dev_priv->dev)) {
-               if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
+               if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
                              EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
                        DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
                        return;
@@ -567,11 +567,11 @@ static void intel_psr_exit(struct drm_device *dev)
                return;
 
        if (HAS_DDI(dev)) {
-               val = I915_READ(EDP_PSR_CTL(dev));
+               val = I915_READ(EDP_PSR_CTL);
 
                WARN_ON(!(val & EDP_PSR_ENABLE));
 
-               I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
+               I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
        } else {
                val = I915_READ(VLV_PSRCTL(pipe));
 
@@ -752,6 +752,9 @@ void intel_psr_init(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
 
+       dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
+               HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
+
        INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
        mutex_init(&dev_priv->psr.lock);
 }