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[GlobalISel][X86] G_BR instruction select test
authorIgor Breger <igor.breger@intel.com>
Mon, 15 May 2017 07:03:38 +0000 (07:03 +0000)
committerIgor Breger <igor.breger@intel.com>
Mon, 15 May 2017 07:03:38 +0000 (07:03 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303036 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/X86/GlobalISel/br.ll [new file with mode: 0644]
test/CodeGen/X86/GlobalISel/select-br.mir [new file with mode: 0644]

diff --git a/test/CodeGen/X86/GlobalISel/br.ll b/test/CodeGen/X86/GlobalISel/br.ll
new file mode 100644 (file)
index 0000000..faa6a03
--- /dev/null
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=x86_64-linux-gnu    -global-isel %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X64
+
+define void @uncondbr() {
+; CHECK-LABEL: uncondbr:
+; CHECK:       # BB#1: # %entry
+; CHECK-NEXT:    jmp .LBB0_3
+; CHECK-NEXT:  .LBB0_2: # %end
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB0_3: # %bb2
+; CHECK-NEXT:    jmp .LBB0_2
+entry:
+  br label %bb2
+end:
+  ret void
+bb2:
+  br label %end
+}
+
diff --git a/test/CodeGen/X86/GlobalISel/select-br.mir b/test/CodeGen/X86/GlobalISel/select-br.mir
new file mode 100644 (file)
index 0000000..6d8cd2b
--- /dev/null
@@ -0,0 +1,39 @@
+# RUN: llc -mtriple=x86_64-linux-gnu    -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X64
+# RUN: llc -mtriple=i386-linux-gnu      -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X32
+
+--- |
+  define void @uncondbr() {
+  entry:
+    br label %bb2
+
+  end:                                              ; preds = %bb2
+    ret void
+
+  bb2:                                              ; preds = %entry
+    br label %end
+  }
+
+...
+---
+name:            uncondbr
+# CHECK-LABEL: name:  uncondbr
+alignment:       4
+legalized:       true
+regBankSelected: true
+# CHECK:     JMP_1 %bb.2.bb2
+# CHECK:     JMP_1 %bb.1.end
+body:             |
+  bb.1.entry:
+    successors: %bb.3.bb2(0x80000000)
+
+    G_BR %bb.3.bb2
+
+  bb.2.end:
+    RET 0
+
+  bb.3.bb2:
+    successors: %bb.2.end(0x80000000)
+
+    G_BR %bb.2.end
+
+...