pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */
pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
- c[0x04] = 0x00; /* pcicmd pci command rw, ro */
- c[0x05] = 0x00;
+ /* TODO: no need to override */
+ c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
+ c[PCI_COMMAND + 1] = 0x00;
- c[0x06] = 0x80; /* pcists pci status rwc, ro */
- c[0x07] = 0x02;
+ /* TODO: */
+ c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
+ c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
- c[0x08] = 0x01; /* rid revision ro */
- c[0x09] = 0x00; /* pi programming interface ro */
+ c[PCI_REVISION_ID] = 0x01; /* rid revision ro */
+ c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
c[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* headtyp header type ro */
- c[0x10] = 0x01; /* nabmar native audio mixer base
- address rw */
- c[0x11] = 0x00;
- c[0x12] = 0x00;
- c[0x13] = 0x00;
-
- c[0x14] = 0x01; /* nabmbar native audio bus mastering
- base address rw */
- c[0x15] = 0x00;
- c[0x16] = 0x00;
- c[0x17] = 0x00;
-
- c[0x2c] = 0x86; /* svid subsystem vendor id rwo */
- c[0x2d] = 0x80;
-
- c[0x2e] = 0x00; /* sid subsystem id rwo */
- c[0x2f] = 0x00;
-
- c[0x3c] = 0x00; /* intr_ln interrupt line rw */
- c[0x3d] = 0x01; /* intr_pn interrupt pin ro */
+ /* TODO set when bar is registered. no need to override. */
+ /* nabmar native audio mixer base address rw */
+ c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
+ c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
+ c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
+ c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
+
+ /* TODO set when bar is registered. no need to override. */
+ /* nabmbar native audio bus mastering base address rw */
+ c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
+ c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
+ c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
+ c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
+
+ c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86; /* svid subsystem vendor id rwo */
+ c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
+
+ c[PCI_SUBSYSTEM_ID] = 0x00; /* sid subsystem id rwo */
+ c[PCI_SUBSYSTEM_ID + 1] = 0x00;
+
+ c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
+ /* TODO: RST# value should be 0. */
+ c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
pci_register_bar (&s->dev, 0, 256 * 4, PCI_BASE_ADDRESS_SPACE_IO,
ac97_map);