\r
main_p : process (input_clk, rst_n)\r
variable plt_step_cnt, nt_step_cnt : integer;\r
+\r
+procedure vram_set (ad: in integer; dt : in integer) is\r
+begin\r
+ r_nw <= '0';\r
+ addr <= conv_std_logic_vector(ad, 16);\r
+ d_io <= conv_std_logic_vector(dt, 8);\r
+end;\r
+procedure vram_clr is\r
+begin\r
+ addr <= (others => 'Z');\r
+ d_io <= (others => 'Z');\r
+ r_nw <= '1';\r
+end;\r
+\r
begin\r
if (rst_n = '0') then\r
init_done <= '0';\r
\r
\r
if (plt_step_cnt = 0) then\r
- addr <= conv_std_logic_vector(16#2006#, 16);\r
- d_io <= conv_std_logic_vector(16#3f#, 8);\r
- r_nw <= '0';\r
- plt_step_cnt := plt_step_cnt + 1;\r
- elsif (plt_step_cnt = 1) then\r
- d_io <= conv_std_logic_vector(16#00#, 8);\r
- plt_step_cnt := plt_step_cnt + 1;\r
-\r
+ --set vram addr 3f00\r
+ vram_set(16#2006#, 16#3f#);\r
elsif (plt_step_cnt = 2) then\r
- addr <= conv_std_logic_vector(16#2007#, 16);\r
- d_io <= conv_std_logic_vector(16#0f#, 8);\r
- plt_step_cnt := plt_step_cnt + 1;\r
- elsif (plt_step_cnt = 3) then\r
- d_io <= conv_std_logic_vector(16#00#, 8);\r
- plt_step_cnt := plt_step_cnt + 1;\r
+ vram_set(16#2006#, 16#00#);\r
+\r
elsif (plt_step_cnt = 4) then\r
- d_io <= conv_std_logic_vector(16#10#, 8);\r
- plt_step_cnt := plt_step_cnt + 1;\r
- elsif (plt_step_cnt = 5) then\r
- d_io <= conv_std_logic_vector(16#20#, 8);\r
- plt_step_cnt := plt_step_cnt + 1;\r
+ --set palette data\r
+ vram_set(16#2007#, 16#0f#);\r
+ elsif (plt_step_cnt = 6) then\r
+ vram_set(16#2007#, 16#00#);\r
+ elsif (plt_step_cnt = 8) then\r
+ vram_set(16#2007#, 16#10#);\r
+ elsif (plt_step_cnt = 10) then\r
+ vram_set(16#2007#, 16#20#);\r
\r
else\r
- addr <= (others => 'Z');\r
- d_io <= (others => 'Z');\r
- r_nw <= '1';\r
- global_step_cnt <= global_step_cnt + 1;\r
+ vram_clr;\r
+ if (plt_step_cnt > 10) then\r
+ global_step_cnt <= global_step_cnt + 1;\r
+ end if;\r
end if;\r
+ plt_step_cnt := plt_step_cnt + 1;\r
\r
elsif (global_step_cnt = 1) then\r
--step1 = name table set.\r
\r
if (nt_step_cnt = 0) then\r
- addr <= conv_std_logic_vector(16#2006#, 16);\r
- d_io <= conv_std_logic_vector(16#20#, 8);\r
- r_nw <= '0';\r
- nt_step_cnt := nt_step_cnt + 1;\r
- elsif (nt_step_cnt = 1) then\r
- d_io <= conv_std_logic_vector(16#00#, 8);\r
- nt_step_cnt := nt_step_cnt + 1;\r
-\r
+ --set vram addr 2000\r
+ vram_set(16#2006#, 16#20#);\r
elsif (nt_step_cnt = 2) then\r
- addr <= conv_std_logic_vector(16#2007#, 16);\r
- d_io <= conv_std_logic_vector(16#41#, 8);\r
- nt_step_cnt := nt_step_cnt + 1;\r
- elsif (nt_step_cnt = 3) then\r
- d_io <= conv_std_logic_vector(16#42#, 8);\r
- nt_step_cnt := nt_step_cnt + 1;\r
+ vram_set(16#2006#, 16#00#);\r
+\r
elsif (nt_step_cnt = 4) then\r
- d_io <= conv_std_logic_vector(16#43#, 8);\r
- nt_step_cnt := nt_step_cnt + 1;\r
+ --set name tbl data\r
+ vram_set(16#2007#, 16#41#);\r
+ elsif (nt_step_cnt = 6) then\r
+ vram_set(16#2007#, 16#42#);\r
+ elsif (nt_step_cnt = 8) then\r
+ vram_set(16#2007#, 16#43#);\r
\r
else\r
- addr <= (others => 'Z');\r
- d_io <= (others => 'Z');\r
- r_nw <= '1';\r
- global_step_cnt <= global_step_cnt + 1;\r
+ vram_clr;\r
+ if (nt_step_cnt > 8) then\r
+ global_step_cnt <= global_step_cnt + 1;\r
+ end if;\r
end if;\r
+ nt_step_cnt := nt_step_cnt + 1;\r
+ \r
else\r
init_done <= '1';\r
end if;\r
add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_addr\r
add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_d_io\r
\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_instruction\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_int_d_bus\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_instruction\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_int_d_bus\r
\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_exec_cycle\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_exec_cycle\r
\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ea_carry \r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_wait_a58_branch_next \r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_ea_carry \r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_wait_a58_branch_next \r
\r
\r
-add wave -divider regs\r
+#add wave -divider regs\r
\r
-#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_index_bus;\r
-#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc_bus;\r
-## dbg_pcl, dbg_pch, \r
-\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_status\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_x\r
-add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_y\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_status\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_x\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/dbg_y\r
\r
\r
add wave -divider ppu\r