drm/msm/dpu: simplify blend configuration

Rewrite dpu_hw_ctl_setup_blendstage() to use static data configuration
rather than using a switch-case. This simplifies adding support for new
pipes.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550
Patchwork: https://patchwork.freedesktop.org/patch/518485/
Link: https://lore.kernel.org/r/20230116063316.728496-3-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 3006296..b88a2f3 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -379,14 +379,37 @@ static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx)
        DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
 }
 
+struct ctl_blend_config {
+       int idx, shift, ext_shift;
+};
+
+static const struct ctl_blend_config ctl_blend_config[][2] = {
+       [SSPP_NONE] = { { -1 }, { -1 } },
+       [SSPP_MAX] =  { { -1 }, { -1 } },
+       [SSPP_VIG0] = { { 0, 0,  0  }, { 3, 0 } },
+       [SSPP_VIG1] = { { 0, 3,  2  }, { 3, 4 } },
+       [SSPP_VIG2] = { { 0, 6,  4  }, { 3, 8 } },
+       [SSPP_VIG3] = { { 0, 26, 6  }, { 3, 12 } },
+       [SSPP_RGB0] = { { 0, 9,  8  }, { -1 } },
+       [SSPP_RGB1] = { { 0, 12, 10 }, { -1 } },
+       [SSPP_RGB2] = { { 0, 15, 12 }, { -1 } },
+       [SSPP_RGB3] = { { 0, 29, 14 }, { -1 } },
+       [SSPP_DMA0] = { { 0, 18, 16 }, { 2, 8 } },
+       [SSPP_DMA1] = { { 0, 21, 18 }, { 2, 12 } },
+       [SSPP_DMA2] = { { 2, 0      }, { 2, 16 } },
+       [SSPP_DMA3] = { { 2, 4      }, { 2, 20 } },
+       [SSPP_DMA4] = { { 4, 0      }, { 4, 8 } },
+       [SSPP_DMA5] = { { 4, 4      }, { 4, 12 } },
+       [SSPP_CURSOR0] =  { { 1, 20 }, { -1 } },
+       [SSPP_CURSOR1] =  { { 1, 26 }, { -1 } },
+};
+
 static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
        enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg)
 {
        struct dpu_hw_blk_reg_map *c = &ctx->hw;
        u32 mix, ext, mix_ext;
-       u32 mixercfg = 0, mixercfg_ext = 0;
-       u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0;
-       u32 mixercfg_ext4 = 0;
+       u32 mixercfg[5] = { 0 };
        int i, j;
        int stages;
        int pipes_per_stage;
@@ -401,7 +424,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
        else
                pipes_per_stage = 1;
 
-       mixercfg = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */
+       mixercfg[0] = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */
 
        if (!stage_cfg)
                goto exit;
@@ -415,119 +438,30 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
                for (j = 0 ; j < pipes_per_stage; j++) {
                        enum dpu_sspp_multirect_index rect_index =
                                stage_cfg->multirect_index[i][j];
-
-                       switch (stage_cfg->stage[i][j]) {
-                       case SSPP_VIG0:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext3 |= mix_ext << 0;
-                               } else {
-                                       mixercfg |= mix << 0;
-                                       mixercfg_ext |= ext << 0;
-                               }
-                               break;
-                       case SSPP_VIG1:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext3 |= mix_ext << 4;
-                               } else {
-                                       mixercfg |= mix << 3;
-                                       mixercfg_ext |= ext << 2;
-                               }
-                               break;
-                       case SSPP_VIG2:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext3 |= mix_ext << 8;
-                               } else {
-                                       mixercfg |= mix << 6;
-                                       mixercfg_ext |= ext << 4;
-                               }
-                               break;
-                       case SSPP_VIG3:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext3 |= mix_ext << 12;
-                               } else {
-                                       mixercfg |= mix << 26;
-                                       mixercfg_ext |= ext << 6;
-                               }
-                               break;
-                       case SSPP_RGB0:
-                               mixercfg |= mix << 9;
-                               mixercfg_ext |= ext << 8;
-                               break;
-                       case SSPP_RGB1:
-                               mixercfg |= mix << 12;
-                               mixercfg_ext |= ext << 10;
-                               break;
-                       case SSPP_RGB2:
-                               mixercfg |= mix << 15;
-                               mixercfg_ext |= ext << 12;
-                               break;
-                       case SSPP_RGB3:
-                               mixercfg |= mix << 29;
-                               mixercfg_ext |= ext << 14;
-                               break;
-                       case SSPP_DMA0:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext2 |= mix_ext << 8;
-                               } else {
-                                       mixercfg |= mix << 18;
-                                       mixercfg_ext |= ext << 16;
-                               }
-                               break;
-                       case SSPP_DMA1:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext2 |= mix_ext << 12;
-                               } else {
-                                       mixercfg |= mix << 21;
-                                       mixercfg_ext |= ext << 18;
-                               }
-                               break;
-                       case SSPP_DMA2:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext2 |= mix_ext << 16;
-                               } else {
-                                       mixercfg_ext2 |= mix_ext << 0;
-                               }
-                               break;
-                       case SSPP_DMA3:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext2 |= mix_ext << 20;
-                               } else {
-                                       mixercfg_ext2 |= mix_ext << 4;
-                               }
-                               break;
-                       case SSPP_DMA4:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext4 |= mix_ext << 8;
-                               } else {
-                                       mixercfg_ext4 |= mix_ext << 0;
-                               }
-                               break;
-                       case SSPP_DMA5:
-                               if (rect_index == DPU_SSPP_RECT_1) {
-                                       mixercfg_ext4 |= mix_ext << 12;
-                               } else {
-                                       mixercfg_ext4 |= mix_ext << 4;
-                               }
-                               break;
-                       case SSPP_CURSOR0:
-                               mixercfg_ext |= mix_ext << 20;
-                               break;
-                       case SSPP_CURSOR1:
-                               mixercfg_ext |= mix_ext << 26;
-                               break;
-                       default:
-                               break;
+                       enum dpu_sspp pipe = stage_cfg->stage[i][j];
+                       const struct ctl_blend_config *cfg =
+                               &ctl_blend_config[pipe][rect_index == DPU_SSPP_RECT_1];
+
+                       /*
+                        * CTL_LAYER has 3-bit field (and extra bits in EXT register),
+                        * all EXT registers has 4-bit fields.
+                        */
+                       if (cfg->idx == 0) {
+                               mixercfg[0] |= mix << cfg->shift;
+                               mixercfg[1] |= ext << cfg->ext_shift;
+                       } else {
+                               mixercfg[cfg->idx] |= mix_ext << cfg->shift;
                        }
                }
        }
 
 exit:
-       DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg);
-       DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);
-       DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);
-       DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3);
+       DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg[0]);
+       DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]);
+       DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]);
+       DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]);
        if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features)))
-               DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg_ext4);
+               DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]);
 }