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drm/amdgpu: revert "Add support for filling a buffer with 64 bit value"
authorChristian König <christian.koenig@amd.com>
Wed, 24 Jan 2018 18:58:45 +0000 (19:58 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 19 Feb 2018 19:18:55 +0000 (14:18 -0500)
This reverts commit 7bdc53f925af085ffa0580f10489f82b36cc2f1c and commit
330df03b3abf944f8f5180f2abc61367749984c0.

Neither are needed any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/si_dma.c

index 8cf2e03..a1f7381 100644 (file)
@@ -319,13 +319,6 @@ struct amdgpu_vm_pte_funcs {
        void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
                          uint64_t value, unsigned count,
                          uint32_t incr);
-
-       /* maximum nums of PTEs/PDEs in a single operation */
-       uint32_t        set_max_nums_pte_pde;
-
-       /* number of dw to reserve per operation */
-       unsigned        set_pte_pde_num_dw;
-
        /* for linear pte/pde updates without addr mapping */
        void (*set_pte_pde)(struct amdgpu_ib *ib,
                            uint64_t pe,
index d4339fe..a021de9 100644 (file)
@@ -1681,13 +1681,12 @@ error_free:
 }
 
 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
-                      uint64_t src_data,
+                      uint32_t src_data,
                       struct reservation_object *resv,
                       struct dma_fence **fence)
 {
        struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-       uint32_t max_bytes = 8 *
-                       adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
+       uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
        struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 
        struct drm_mm_node *mm_node;
@@ -1718,9 +1717,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
                num_pages -= mm_node->size;
                ++mm_node;
        }
-
-       /* num of dwords for each SDMA_OP_PTEPDE cmd */
-       num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
+       num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
 
        /* for IB padding */
        num_dw += 64;
@@ -1745,16 +1742,12 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
                uint32_t byte_count = mm_node->size << PAGE_SHIFT;
                uint64_t dst_addr;
 
-               WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
-
                dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
                while (byte_count) {
                        uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
 
-                       amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
-                                       dst_addr, 0,
-                                       cur_size_in_bytes >> 3, 0,
-                                       src_data);
+                       amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
+                                               dst_addr, cur_size_in_bytes);
 
                        dst_addr += cur_size_in_bytes;
                        byte_count -= cur_size_in_bytes;
index 167856f..1e275c7 100644 (file)
@@ -86,7 +86,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
                               struct reservation_object *resv,
                               struct dma_fence **f);
 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
-                       uint64_t src_data,
+                       uint32_t src_data,
                        struct reservation_object *resv,
                        struct dma_fence **fence);
 
index cecdb21..e584c20 100644 (file)
@@ -1242,11 +1242,10 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 
        } else {
                /* set page commands needed */
-               ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
+               ndw += ncmds * 10;
 
                /* extra commands for begin/end fragments */
-               ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw
-                               * adev->vm_manager.fragment_size;
+               ndw += 2 * 10 * adev->vm_manager.fragment_size;
 
                params.func = amdgpu_vm_do_set_ptes;
        }
index 5d18512..d78bf18 100644 (file)
@@ -1382,9 +1382,6 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
        .copy_pte = cik_sdma_vm_copy_pte,
 
        .write_pte = cik_sdma_vm_write_pte,
-
-       .set_max_nums_pte_pde = 0x1fffff >> 3,
-       .set_pte_pde_num_dw = 10,
        .set_pte_pde = cik_sdma_vm_set_pte_pde,
 };
 
index 6a7a82a..792774e 100644 (file)
@@ -1306,9 +1306,6 @@ static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
        .copy_pte = sdma_v2_4_vm_copy_pte,
 
        .write_pte = sdma_v2_4_vm_write_pte,
-
-       .set_max_nums_pte_pde = 0x1fffff >> 3,
-       .set_pte_pde_num_dw = 10,
        .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
 };
 
index 88178d8..83dde3b 100644 (file)
@@ -1739,10 +1739,6 @@ static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
        .copy_pte = sdma_v3_0_vm_copy_pte,
 
        .write_pte = sdma_v3_0_vm_write_pte,
-
-       /* not 0x3fffff due to HW limitation */
-       .set_max_nums_pte_pde = 0x3fffe0 >> 3,
-       .set_pte_pde_num_dw = 10,
        .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
 };
 
index e9b1b83..8505458 100644 (file)
@@ -1686,9 +1686,6 @@ static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
        .copy_pte = sdma_v4_0_vm_copy_pte,
 
        .write_pte = sdma_v4_0_vm_write_pte,
-
-       .set_max_nums_pte_pde = 0x400000 >> 3,
-       .set_pte_pde_num_dw = 10,
        .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
 };
 
index e59521b..2db5bfb 100644 (file)
@@ -875,9 +875,6 @@ static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
        .copy_pte = si_dma_vm_copy_pte,
 
        .write_pte = si_dma_vm_write_pte,
-
-       .set_max_nums_pte_pde = 0xffff8 >> 3,
-       .set_pte_pde_num_dw = 9,
        .set_pte_pde = si_dma_vm_set_pte_pde,
 };