llvm-mc/AsmParser: Disambiguate i64i8imm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78598 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index ef52785..5393568 100644 (file)
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -28,7 +28,9 @@ def i64i32imm_pcrel : Operand<i64> {
 
 
 // 64-bits but only 8 bits are significant.
-def i64i8imm   : Operand<i64>;
+def i64i8imm   : Operand<i64> {
+  let ParserMatchClass = ImmSExt8AsmOperand;
+}
 
 def lea64mem : Operand<i64> {
   let PrintMethod = "printlea64mem";

diff --git a/test/MC/AsmParser/x86_instructions.s b/test/MC/AsmParser/x86_instructions.s
index 57d9dec..1ddd9e3 100644 (file)
--- a/test/MC/AsmParser/x86_instructions.s
+++ b/test/MC/AsmParser/x86_instructions.s
@@ -1,6 +1,6 @@
 // FIXME: Switch back to FileCheck once we print actual instructions
         
-// RUN: llvm-mc -triple i386-unknown-unknown %s > %t
+// RUN: llvm-mc -triple x86_64-unknown-unknown %s > %t
 
 // RUN: grep {MCInst(opcode=.*, operands=.reg:2, reg:0, reg:2.)} %t
         subb %al, %al
@@ -29,4 +29,10 @@
 // RUN: grep {MCInst(opcode=.*, operands=.reg:19, reg:0, val:256.)} %t
         subl $256, %eax
 
+// FIXME: Check that this matches XOR64ri8
+// RUN: grep {MCInst(opcode=.*, operands=.reg:19, reg:0, val:1.)} %t
+        xorq $1, %eax
         
+// FIXME: Check that this matches XOR64ri32
+// RUN: grep {MCInst(opcode=.*, operands=.reg:19, reg:0, val:256.)} %t
+        xorq $256, %eax