[ARM] Added FP16 VREV Vector Instrinsic CodeGen support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339546 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 7f2ebcd..5a300c7 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -6589,6 +6589,8 @@ def VREV64q8  : VREV64Q<0b00, "vrev64", "8", v16i8>;
 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
+def : Pat<(v8f16 (NEONvrev64 (v8f16 QPR:$Vm))), (VREV64q16 QPR:$Vm)>;
+def : Pat<(v4f16 (NEONvrev64 (v4f16 DPR:$Vm))), (VREV64d16 DPR:$Vm)>;
 
 //   VREV32   : Vector Reverse elements within 32-bit words
 

diff --git a/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll b/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
index dc0f4a9..a9c5838 100644 (file)
--- a/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
+++ b/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
@@ -1213,19 +1213,17 @@ entry:
   ret <8 x half> %vext
 }
 
-; FIXME (PR38404)
-;
-;define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {
-;entry:
-;  %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-;  ret <4 x half> %shuffle.i
-;}
-;
-;define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
-;entry:
-;  %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
-;  ret <8 x half> %shuffle.i
-;}
+define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {
+entry:
+  %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x half> %shuffle.i
+}
+
+define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
+entry:
+  %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x half> %shuffle.i
+}
 
 declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)