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[mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backend
authorZoran Jovanovic <zoran.jovanovic@imgtec.com>
Fri, 2 Oct 2015 13:06:02 +0000 (13:06 +0000)
committerZoran Jovanovic <zoran.jovanovic@imgtec.com>
Fri, 2 Oct 2015 13:06:02 +0000 (13:06 +0000)
Differential Revision: http://reviews.llvm.org/D13235

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249123 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsInstrFPU.td
test/CodeGen/Mips/llvm-ir/sqrt.ll [new file with mode: 0644]

index 9b9d5f6..d1a7249 100644 (file)
@@ -353,11 +353,8 @@ def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
 
-let AdditionalPredicates = [NotInMicroMips] in {
-def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>,
-              ABSS_FM<0x4, 16>, ISA_MIPS2;
-}
-
+def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
+              II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
 
 // The odd-numbered registers are only referenced when doing loads,
diff --git a/test/CodeGen/Mips/llvm-ir/sqrt.ll b/test/CodeGen/Mips/llvm-ir/sqrt.ll
new file mode 100644 (file)
index 0000000..1a8892d
--- /dev/null
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
+; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s
+
+define float @sqrt_fn(float %value) #0 {
+entry:
+  %sqrtf = tail call float @sqrtf(float %value) #0
+  ret float %sqrtf
+}
+
+declare float @sqrtf(float)
+
+; CHECK: sqrt.s $f0, $f12