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drm/msm/adreno: Use quirk identify hw_apriv
authorRob Clark <robdclark@chromium.org>
Thu, 27 Jul 2023 21:20:09 +0000 (14:20 -0700)
committerRob Clark <robdclark@chromium.org>
Mon, 7 Aug 2023 21:19:16 +0000 (14:19 -0700)
Rather than just open coding a list of gpu-id matches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549764/

drivers/gpu/drm/msm/adreno/a6xx_gpu.c
drivers/gpu/drm/msm/adreno/adreno_device.c
drivers/gpu/drm/msm/adreno/adreno_gpu.h

index 5ba8b5a..6f8c438 100644 (file)
@@ -2489,8 +2489,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
        /* Quirk data */
        adreno_gpu->info = info;
 
-       if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
-               adreno_gpu->base.hw_apriv = true;
+       adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
 
        a6xx_llc_slices_init(pdev, a6xx_gpu);
 
index 3269122..f469f95 100644 (file)
@@ -302,6 +302,7 @@ static const struct adreno_info gpulist[] = {
                },
                .gmem = SZ_1M + SZ_128K,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
                .init = a6xx_gpu_init,
                .zapfw = "a650_zap.mdt",
                .hwcg = a650_hwcg,
@@ -315,6 +316,7 @@ static const struct adreno_info gpulist[] = {
                },
                .gmem = SZ_1M + SZ_512K,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
                .init = a6xx_gpu_init,
                .zapfw = "a660_zap.mdt",
                .hwcg = a660_hwcg,
@@ -327,6 +329,7 @@ static const struct adreno_info gpulist[] = {
                },
                .gmem = SZ_512K,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
                .init = a6xx_gpu_init,
                .hwcg = a660_hwcg,
                .address_space_size = SZ_16G,
@@ -350,6 +353,7 @@ static const struct adreno_info gpulist[] = {
                },
                .gmem = SZ_4M,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
                .init = a6xx_gpu_init,
                .zapfw = "a690_zap.mdt",
                .hwcg = a690_hwcg,
index 922f3de..14d7f75 100644 (file)
@@ -32,6 +32,7 @@ enum {
 #define ADRENO_QUIRK_TWO_PASS_USE_WFI          BIT(0)
 #define ADRENO_QUIRK_FAULT_DETECT_MASK         BIT(1)
 #define ADRENO_QUIRK_LMLOADKILL_DISABLE                BIT(2)
+#define ADRENO_QUIRK_HAS_HW_APRIV              BIT(3)
 
 struct adreno_rev {
        uint8_t  core;