ADXL345

diff --git a/hw/ADXL345.h b/hw/ADXL345.h
new file mode 100644 (file)
index 0000000..b59ced0
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+++ b/hw/ADXL345.h
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+// ADXL345
+
+enum {
+   // flags
+   ADXL_READ  = 1<<7, // Read flag
+   ADXL_WRITE = 0<<7, // Write flag
+   ADXL_MULTI = 1<<6, // Multiple-Byte flag
+   // registers
+   ADXL_DEVID = 0, // DEVID register
+   ADXL_DEVID_V = 0xE5, // DEVID value
+
+   ADXL_BW_RATE = 0x2C, // BW_RATE register
+   ADXL_LOW_POWER = 1<<4, // LOW_POWER bit
+   ADXL_RATE_100  = 10<<0, // Output Data Rate = 100Hz
+   ADXL_RATE_25   =  8<<0, // Output Data Rate = 25Hz
+
+   ADXL_POWER_CTL = 0x2D, // POWER_CTL register
+   ADXL_LINK       = 1<<5, // Link bit
+   ADXL_AUTO_SLEEP = 1<<4, // AUTO_SLEEP bit
+   ADXL_MEASURE    = 1<<3, // enable Measurement
+   ADXL_SLEEP      = 1<<2, // Sleep mode
+   ADXL_WAKEUP_8   = 0<<0, // Wakeup frequency = 8Hz
+   ADXL_WAKEUP_4   = 1<<0, // Wakeup frequency = 4Hz
+   ADXL_WAKEUP_2   = 2<<0, // Wakeup frequency = 2Hz
+   ADXL_WAKEUP_1   = 3<<0, // Wakeup frequency = 1Hz
+
+   ADXL_INT_ENABLE = 0x2E, // INT_ENABLE register
+   ADXL_INT_MAP    = 0x2F, // INT_MAP register
+   ADXL_INT_SOURCE = 0x30, // INT_SOURCE register
+   ADXL_INT_OVERRUN    = 1<<0, // Data Overrun
+   ADXL_INT_WATERMARK  = 1<<1, // FIFO Watermark
+   ADXL_INT_FREE_FALL  = 1<<2, // Free Fall
+   ADXL_INT_INACTIVITY = 1<<3, // Inactivity
+   ADXL_INT_ACTIVITY   = 1<<4, // Activity
+   ADXL_INT_DOUBLE_TAP = 1<<5, // Double Tap
+   ADXL_INT_SINGLE_TAP = 1<<6, // Single Tap
+   ADXL_INT_DATA_READY = 1<<7, // Data Ready - new data is available
+
+   ADXL_DATA_FORMAT = 0x31, // DATA_FORMAT register
+   ADXL_SELF_TEST = 1<<7, // SELF_TEST bit
+   ADXL_FULL_RES  = 1<<3, // FULL_RES bit
+   ADXL_JUSTIFY   = 1<<2, // Justify bit
+   ADXL_RANGE_2G  = 0<<0, // Range: +/- 2g
+   ADXL_RANGE_4G  = 1<<0, // Range: +/- 4g
+   ADXL_RANGE_8G  = 2<<0, // Range: +/- 8g
+   ADXL_RANGE_16G = 3<<0, // Range: +/-16g
+
+   ADXL_DATAX0 = 0x32, // DATAX0 register
+
+   ADXL_FIFO_CTL = 0x38, // FIFO_CTL register
+   ADXL_FIFO_BYPASS  = 0<<6, // FIFO Bypass
+   ADXL_FIFO_FIFO    = 1<<6, // FIFO std mode
+   ADXL_FIFO_STREAM  = 2<<6, // FIFO Stream mode
+   ADXL_FIFO_TRIGGER = 3<<6, // FIFO Trigger mode
+
+   ADXL_FIFO_STATUS = 0x39, // FIFO_STATUS register
+};