// Vector reductions
for (MVT VT : { MVT::v4f16, MVT::v2f32,
MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
- setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
- setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
+ if (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()) {
+ setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
+ setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
- if (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16())
setOperationAction(ISD::VECREDUCE_FADD, VT, Legal);
+ }
}
for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
declare half @llvm.vector.reduce.fmax.v1f16(<1 x half> %a)
declare float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a)
declare double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fmax.v1f128(<1 x fp128> %a)
+declare half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fmax.v2f128(<2 x fp128> %a)
declare float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a)
ret fp128 %b
}
+define half @test_v4f16(<4 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v4f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: mov h1, v0.h[3]
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s2
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v4f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
+ ret half %b
+}
+
+define half @test_v4f16_ninf(<4 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v4f16_ninf:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: mov h1, v0.h[3]
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s2
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v4f16_ninf:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fmaxnmv h0, v0.4h
+; CHECK-FP-NEXT: ret
+ %b = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a)
+ ret half %b
+}
+
define float @test_v3f32(<3 x float> %a) nounwind {
; CHECK-LABEL: test_v3f32:
; CHECK: // %bb.0:
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
+declare half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
ret fp128 %b
}
+define half @test_v4f16(<4 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v4f16:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: mov h1, v0.h[3]
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fminnm s0, s0, s3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fminnm s0, s0, s2
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v4f16:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fminnmv h0, v0.4h
+; CHECK-FP-NEXT: ret
+ %b = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
+ ret half %b
+}
+
+define half @test_v4f16_ninf(<4 x half> %a) nounwind {
+; CHECK-NOFP-LABEL: test_v4f16_ninf:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NOFP-NEXT: mov h3, v0.h[1]
+; CHECK-NOFP-NEXT: mov h1, v0.h[3]
+; CHECK-NOFP-NEXT: mov h2, v0.h[2]
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s3, h3
+; CHECK-NOFP-NEXT: fminnm s0, s0, s3
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s2, h2
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fminnm s0, s0, s2
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: fcvt s0, h0
+; CHECK-NOFP-NEXT: fcvt s1, h1
+; CHECK-NOFP-NEXT: fminnm s0, s0, s1
+; CHECK-NOFP-NEXT: fcvt h0, s0
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-FP-LABEL: test_v4f16_ninf:
+; CHECK-FP: // %bb.0:
+; CHECK-FP-NEXT: fminnmv h0, v0.4h
+; CHECK-FP-NEXT: ret
+ %b = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
+ ret half %b
+}
+
define float @test_v3f32(<3 x float> %a) nounwind {
; CHECK-LABEL: test_v3f32:
; CHECK: // %bb.0: