rts ok

diff --git a/simulation/cpu/alu.vhd b/simulation/cpu/alu.vhd
index 6047a26..18059c9 100644 (file)
--- a/simulation/cpu/alu.vhd
+++ b/simulation/cpu/alu.vhd
@@ -137,6 +137,7 @@ entity alu is
             pch_inc_n       : in std_logic;
             sph_oe_n        : in std_logic;
             sp_push_n       : in std_logic;
+            sp_pop_n        : in std_logic;
             abs_ea_n        : in std_logic;
             zp_ea_n         : in std_logic;
             arith_en_n      : in std_logic;
@@ -269,9 +270,20 @@ begin
         --stack operation...
         abh <= "00000001";
 
-        if (sp_push_n /= '0') then
+        if (sp_push_n /= '0' and sp_pop_n /= '0') then
             abl <= bal;
+        elsif (sp_pop_n = '0') then
+            sel <= ALU_INC;
+            d1 <= bal;
+            alu_res <= d_out;
+
+            if (clk = '0') then
+                abl <= bal;
+            else
+                abl <= bal_reg;
+            end if;
         else
+            ---case push
             sel <= ALU_DEC;
             d1 <= bal;
             alu_res <= d_out;

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 7d8977a..d374403 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -30,6 +30,7 @@ entity decoder is
             sp_cmd          : out std_logic_vector(3 downto 0);
             sph_oe_n        : out std_logic;
             sp_push_n       : out std_logic;
+            sp_pop_n        : out std_logic;
             acc_cmd         : out std_logic_vector(3 downto 0);
             x_cmd           : out std_logic_vector(3 downto 0);
             y_cmd           : out std_logic_vector(3 downto 0);
@@ -183,6 +184,7 @@ begin
     sp_cmd <= "1111";
     sph_oe_n <= '1';
     sp_push_n <= '1';
+    sp_pop_n <= '1';
     acc_cmd <= "1111";
     x_cmd <= "1111";
     y_cmd <= "1111";
@@ -1108,6 +1110,68 @@ end  procedure;
                 -- A.5.7 return from soubroutine
                 ----------------------------------------
                 elsif instruction = conv_std_logic_vector(16#60#, dsize) then
+                    if exec_cycle = T1 then
+                        d_print("rts 2");
+                        back_oe(pcl_cmd, '1');
+                        back_oe(pch_cmd, '1');
+                        pcl_inc_n <= '1';
+
+                        --pop stack (decrement only)
+                        back_oe(sp_cmd, '0');
+                        back_we(sp_cmd, '0');
+                        sp_pop_n <= '0';
+                        sph_oe_n <= '0';
+
+                        next_cycle <= T2;
+                    elsif exec_cycle = T2 then
+                        d_print("rts 3");
+
+                        --pop pcl
+                        back_oe(sp_cmd, '0');
+                        back_we(sp_cmd, '0');
+                        sp_pop_n <= '0';
+                        sph_oe_n <= '0';
+
+                        --load lo addr.
+                        dbuf_int_oe_n <= '0';
+                        front_we(pcl_cmd, '0');
+
+                        next_cycle <= T3;
+                    elsif exec_cycle = T3 then
+                        d_print("rts 4");
+                        --stack decrement stop.
+                        back_we(sp_cmd, '1');
+                        sp_pop_n <= '1';
+                        front_we(pcl_cmd, '1');
+
+                        --pop pch
+                        back_oe(sp_cmd, '0');
+                        sph_oe_n <= '0';
+                        --load hi addr.
+                        dbuf_int_oe_n <= '0';
+                        front_we(pch_cmd, '0');
+
+                        next_cycle <= T4;
+                    elsif exec_cycle = T4 then
+                        d_print("rts 5");
+                        back_oe(sp_cmd, '1');
+                        sph_oe_n <= '1';
+                        --load hi addr.
+                        dbuf_int_oe_n <= '1';
+                        front_we(pch_cmd, '1');
+                        --empty cycle.
+                        --complying h/w manual...
+                        next_cycle <= T5;
+                    elsif exec_cycle = T5 then
+                        d_print("rts 6");
+
+                        --increment pc.
+                        pcl_inc_n <= '0';
+                        back_we(pcl_cmd, '0');
+                        back_oe(pcl_cmd, '0');
+                        back_oe(pch_cmd, '0');
+                        next_cycle <= T0;
+                    end if; --if exec_cycle = T1 then
 
                 ----------------------------------------
                 -- A.5.8 branch operations
@@ -1161,6 +1225,7 @@ end  procedure;
                 sp_cmd <= "1111";
                 sph_oe_n <= '1';
                 sp_push_n <= '1';
+                sp_pop_n <= '1';
                 acc_cmd <= "1111";
                 x_cmd <= "1111";
                 y_cmd <= "1111";

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index bc2799d..de6c607 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -51,6 +51,7 @@ component decoder
             sp_cmd          : out std_logic_vector(3 downto 0);
             sph_oe_n        : out std_logic;
             sp_push_n       : out std_logic;
+            sp_pop_n        : out std_logic;
             acc_cmd         : out std_logic_vector(3 downto 0);
             x_cmd           : out std_logic_vector(3 downto 0);
             y_cmd           : out std_logic_vector(3 downto 0);
@@ -75,6 +76,7 @@ component alu
             pch_inc_n       : in std_logic;
             sph_oe_n        : in std_logic;
             sp_push_n       : in std_logic;
+            sp_pop_n        : in std_logic;
             abs_ea_n        : in std_logic;
             zp_ea_n         : in std_logic;
             arith_en_n      : in std_logic;
@@ -235,6 +237,7 @@ end component;
     signal y_cmd : std_logic_vector(3 downto 0);
     signal sph_oe_n : std_logic;
     signal sp_push_n : std_logic;
+    signal sp_pop_n  : std_logic;
 
     ---status register
     signal stat_dec_oe_n : std_logic;
@@ -327,6 +330,7 @@ begin
                     sp_cmd,
                     sph_oe_n,
                     sp_push_n,
+                    sp_pop_n,
                     acc_cmd,
                     x_cmd,
                     y_cmd,
@@ -347,6 +351,7 @@ begin
                     pch_inc_n,
                     sph_oe_n,
                     sp_push_n,
+                    sp_pop_n,
                     abs_ea_n,
                     zp_ea_n,
                     arith_en_n,