spi-atmel: support inter-word delay

If the SPI slave requires an inter-word delay, configure the DLYBCT
register accordingly.

Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
board).

Signed-off-by: Jonas Bonn <jonas@norrbonn.se>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
CC: Nicolas Ferre <nicolas.ferre@microchip.com>
CC: Mark Brown <broonie@kernel.org>
CC: Alexandre Belloni <alexandre.belloni@bootlin.com>
CC: Ludovic Desroches <ludovic.desroches@microchip.com>
CC: linux-spi@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index f53f0c5..4954f0a 100644 (file)
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -1201,13 +1201,14 @@ static int atmel_spi_setup(struct spi_device *spi)
                csr |= SPI_BIT(CSAAT);
 
        /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
-        *
-        * DLYBCT would add delays between words, slowing down transfers.
-        * It could potentially be useful to cope with DMA bottlenecks, but
-        * in those cases it's probably best to just use a lower bitrate.
         */
        csr |= SPI_BF(DLYBS, 0);
-       csr |= SPI_BF(DLYBCT, 0);
+
+       /* DLYBCT adds delays between words.  This is useful for slow devices
+        * that need a bit of time to setup the next transfer.
+        */
+       csr |= SPI_BF(DLYBCT,
+                       (as->spi_clk / 1000000 * spi->word_delay_usecs) >> 5);
 
        asd = spi->controller_state;
        if (!asd) {