--timing adjust
signal io_cnt : std_logic_vector(0 downto 0);
+signal vram_io : std_logic;
--vram i/o
signal io_oe_n : std_logic;
signal cur_y : std_logic_vector(X_SIZE - 1 downto 0);
signal next_x : std_logic_vector(X_SIZE - 1 downto 0);
signal next_y : std_logic_vector(X_SIZE - 1 downto 0);
+signal scrl_x : std_logic_vector(X_SIZE - 1 downto 0);
+signal scrl_y : std_logic_vector(X_SIZE - 1 downto 0);
signal nt_we_n : std_logic;
signal disp_nt : std_logic_vector (dsize - 1 downto 0);
cnt_x_en_n <= '0';
- ale <= io_cnt(0) when ppu_mask(PPUSBG) = '1' and
+ vram_io <= io_cnt(0) when ppu_scroll_x(0) = '0' else
+ not io_cnt(0);
+ ale <= vram_io when ppu_mask(PPUSBG) = '1' and
(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or
cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE)) else
- io_cnt(0) when ppu_mask(PPUSSP) = '1' and
+ vram_io when ppu_mask(PPUSSP) = '1' and
(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or
cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE)) else
'Z';
- rd_n <= io_cnt(0) when ppu_mask(PPUSBG) = '1' and
+ rd_n <= vram_io when ppu_mask(PPUSBG) = '1' and
(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or
cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE)) else
- io_cnt(0) when ppu_mask(PPUSSP) = '1' and
+ vram_io when ppu_mask(PPUSSP) = '1' and
(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or
cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE)) else
'Z';
(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or
cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE)) else
'Z';
- io_oe_n <= not io_cnt(0) when ppu_mask(PPUSBG) = '1' and
+ io_oe_n <= not vram_io when ppu_mask(PPUSBG) = '1' and
(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or
cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE)) else
- not io_cnt(0) when ppu_mask(PPUSSP) = '1' and
+ not vram_io when ppu_mask(PPUSSP) = '1' and
(cur_y < conv_std_logic_vector(VSCAN, X_SIZE) or
cur_y = conv_std_logic_vector(VSCAN_MAX - 1, X_SIZE)) else
'1';
io_cnt_inst : counter_register generic map (1, 1)
port map (clk, cnt_x_res_n, '0', '1', (others => '0'), io_cnt);
+ --take scroll position into account
+ scrl_x <= cur_x + ppu_scroll_x
+ when cur_x + ppu_scroll_x <= "101010100" else
+ cur_x + ppu_scroll_x + "110101101";
+
+ scrl_y <= cur_y + ppu_scroll_y
+ when cur_y + ppu_scroll_y <= "100000101" else
+ cur_y + ppu_scroll_y + "111111100";
+
---x pos is 8 cycle ahead of current pos.
- next_x <= cur_x + "000010000"
- when cur_x < conv_std_logic_vector(HSCAN_NEXT_START, X_SIZE) else
- cur_x + "011000000";
+ next_x <= scrl_x + "000010000"
+ when scrl_x < conv_std_logic_vector(HSCAN_NEXT_START, X_SIZE) else
+ scrl_x + "011000000";
next_y <= cur_y
when cur_x <= conv_std_logic_vector(HSCAN, X_SIZE) else
"000000000"
vram_ad(4) & vram_ad(5) & vram_ad(6) & vram_ad(7)) &
disp_ptn_h (dsize downto 1);
- ptn_en_n <= '1' when cur_x = conv_std_logic_vector(0, X_SIZE) else
- '0' when cur_x <= conv_std_logic_vector(HSCAN_NEXT_EXTRA, X_SIZE) else
+ ptn_en_n <= '1' when scrl_x = conv_std_logic_vector(0, X_SIZE) else
+ '0' when scrl_x <= conv_std_logic_vector(HSCAN_NEXT_EXTRA, X_SIZE) else
'1';
ptn_l_inst : d_flip_flop generic map(dsize)
d_print("cur_y: " & conv_hex16(conv_integer(cur_y)));
----fetch next tile byte.
- if (cur_x (2 downto 0) = "001" ) then
+ if (scrl_x (2 downto 0) = "001" ) then
--vram addr is incremented every 8 cycle.
--name table at 0x2000
vram_addr(9 downto 0)
& next_x(dsize - 1 downto 3);
vram_addr(asize - 1 downto 10) <= "10" & ppu_ctrl(PPUBNA downto 0);
end if;
- if (cur_x (2 downto 0) = "010" ) then
+ if (scrl_x (2 downto 0) = "010" ) then
nt_we_n <= '0';
else
nt_we_n <= '1';
end if;
----fetch attr table byte.
- if (cur_x (4 downto 0) = "11011" or
- cur_x = conv_std_logic_vector(HSCAN_NEXT_START + 3, X_SIZE)) then
+ if (scrl_x (4 downto 0) = "11011" or
+ scrl_x = conv_std_logic_vector(HSCAN_NEXT_START + 3, X_SIZE)) then
--attribute table is loaded every 32 cycle.
--attr table at 0x23c0
vram_addr(dsize - 1 downto 0) <= "11000000" +
("00" & next_y(7 downto 5) & next_x(7 downto 5));
vram_addr(asize - 1 downto dsize) <= "10" &
ppu_ctrl(PPUBNA downto 0) & "11";
- end if;--if (cur_x (2 downto 0) = "010" ) then
- if (cur_x (4 downto 0) = "11100" or
- cur_x = conv_std_logic_vector(HSCAN_NEXT_START + 4, X_SIZE)) then
+ end if;--if (scrl_x (2 downto 0) = "010" ) then
+ if (scrl_x (4 downto 0) = "11100" or
+ scrl_x = conv_std_logic_vector(HSCAN_NEXT_START + 4, X_SIZE)) then
attr_we_n <= '0';
else
attr_we_n <= '1';
end if;
- if (cur_x (4 downto 0) = "00000" ) then
+ if (scrl_x (4 downto 0) = "00000" ) then
disp_attr_we_n <= '0';
else
disp_attr_we_n <= '1';
end if;
---attribute is shifted every 16 bit.
- if (cur_x (3 downto 0) = "0000" ) then
+ if (scrl_x (3 downto 0) = "0000" ) then
attr_ce_n <= '0';
else
attr_ce_n <= '1';
cur_x > conv_std_logic_vector(HSCAN_NEXT_START, X_SIZE)) then
----fetch pattern table low byte.
- if (cur_x (2 downto 0) = "101" ) then
+ if (scrl_x (2 downto 0) = "101" ) then
--vram addr is incremented every 8 cycle.
vram_addr <= "0" & ppu_ctrl(PPUBPA) &
disp_nt(dsize - 1 downto 0)
& "0" & next_y(2 downto 0);
- end if;--if (cur_x (2 downto 0) = "100" ) then
- if (cur_x (2 downto 0) = "110" ) then
+ end if;--if (scrl_x (2 downto 0) = "100" ) then
+ if (scrl_x (2 downto 0) = "110" ) then
ptn_l_we_n <= '0';
else
ptn_l_we_n <= '1';
end if;
----fetch pattern table high byte.
- if (cur_x (2 downto 0) = "111" ) then
+ if (scrl_x (2 downto 0) = "111" ) then
--vram addr is incremented every 8 cycle.
vram_addr <= "0" & ppu_ctrl(PPUBPA) &
disp_nt(dsize - 1 downto 0)
& "0" & next_y(2 downto 0) + "00000000001000";
- end if; --if (cur_x (2 downto 0) = "110" ) then
- if (cur_x (2 downto 0) = "000" and cur_x /= "000000000") then
+ end if; --if (scrl_x (2 downto 0) = "110" ) then
+ if (scrl_x (2 downto 0) = "000" and scrl_x /= "000000000") then
ptn_h_we_n <= '0';
else
ptn_h_we_n <= '1';
- end if;--if (cur_x (2 downto 0) = "001" ) then
+ end if;--if (scrl_x (2 downto 0) = "001" ) then
end if; --if (cur_x <= conv_std_logic_vector(HSCAN, X_SIZE)) and
end if;--if (ppu_mask(PPUSBG) = '1') then