const MachineInstrDescriptor &Desc = get(Opcode);
// Print instruction prefixes if neccesary
-
if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
O << "\t\t\t";
O << "-"; MI->print(O, TM);
break;
+
case X86II::RawFrm:
toHex(O, getBaseOpcodeFor(Opcode));
O << "\n\t\t\t\t";
O << "\n";
return;
-
case X86II::AddRegFrm: {
// There are currently two forms of acceptable AddRegFrm instructions.
// Either the instruction JUST takes a single register (like inc, dec, etc),
const MachineInstrDescriptor &Desc = get(Opcode);
// Print instruction prefixes if neccesary
-
if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
O << "\t\t\t";
O << "-"; MI->print(O, TM);
break;
+
case X86II::RawFrm:
toHex(O, getBaseOpcodeFor(Opcode));
O << "\n\t\t\t\t";
O << "\n";
return;
-
case X86II::AddRegFrm: {
// There are currently two forms of acceptable AddRegFrm instructions.
// Either the instruction JUST takes a single register (like inc, dec, etc),