drm/amd/display: Program meta addresses correctly

[Why]
When forcing 3D mode in DAL, we set the right address to be the same as the
left address. We need to do the same for the meta addresses.

[How]
Program right meta to be same as left meta.

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 86a0d46..9528e3a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1535,6 +1535,8 @@ static bool patch_address_for_sbs_tb_stereo(
                        plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
                        plane_state->address.grph_stereo.right_addr =
                        plane_state->address.grph_stereo.left_addr;
+                       plane_state->address.grph_stereo.right_meta_addr =
+                       plane_state->address.grph_stereo.left_meta_addr;
                }
        }
        return false;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 01530e6..04b939f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2034,6 +2034,8 @@ static bool patch_address_for_sbs_tb_stereo(
                plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
                plane_state->address.grph_stereo.right_addr =
                                plane_state->address.grph_stereo.left_addr;
+               plane_state->address.grph_stereo.right_meta_addr =
+                               plane_state->address.grph_stereo.left_meta_addr;
        }
        return false;
 }