def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
+def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
let mayLoad = 0 in {
def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
AtomicNoRet<"ds_add_u32", 1>;
+def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
+ AtomicNoRet<"ds_add_f32", 1>;
def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
AtomicNoRet<"ds_sub_u32", 1>;
def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
+def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>;
def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>;
+def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
-// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
-// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SI --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SI --check-prefix=SICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CI --check-prefix=SICI
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOCI --check-prefix=NOSICI
+
//===----------------------------------------------------------------------===//
// Checks for 16-bit Offsets
//===----------------------------------------------------------------------===//
// SICI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
+ds_add_f32 v2, v4
+// NOSICI: error: instruction not supported on this GPU
+// VI: ds_add_f32 v2, v4 ; encoding: [0x00,0x00,0x2a,0xd8,0x02,0x04,0x00,0x00]
+
ds_sub_u32 v2, v4
// SICI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x02,0xd8,0x02,0x04,0x00,0x00]
// SICI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x80,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08]
+ds_add_rtn_f32 v8, v2, v4
+// NOSICI: error: instruction not supported on this GPU
+// VI: ds_add_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x04,0x00,0x08]
+
ds_sub_rtn_u32 v8, v2, v4
// SICI: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x84,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x42,0xd8,0x02,0x04,0x00,0x08]