int64_t MaxBytesToFill = 15;
- // if there is an arguement
+ // if there is an argument
if (getLexer().isNot(AsmToken::EndOfStatement)) {
const MCExpr *Value;
SMLoc ExprLoc = L;
}
-/// Attempt to coalesce one of the source registers to a MUX intruction with
+/// Attempt to coalesce one of the source registers to a MUX instruction with
/// the destination register. This could lead to having only one predicated
/// instruction in the end instead of two.
bool HexagonExpandCondsets::coalesceSegments(
return false;
}
- // By now, we should have successfuly obtained the immediate value defining
+ // By now, we should have successfully obtained the immediate value defining
// the register referenced in MO. Handle a potential use of a subregister.
switch (MO.getSubReg()) {
case Hexagon::isub_lo:
bits<4> Value = value;
}
-def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
+def NoMemAccess : MemAccessSize<0>;// Not a memory access instruction.
def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
//===----------------------------------------------------------------------===//
//----------------------------------------------------------------------------//
-// Hexagon Intruction Flags +
+// Hexagon Instruction Flags +
//
// *** Must match BaseInfo.h ***
//----------------------------------------------------------------------------//
def TypeCVI_VM_STU : IType<27>;
def TypeCVI_HIST : IType<28>;
//----------------------------------------------------------------------------//
-// Intruction Classes Definitions +
+// Instruction Classes Definitions +
//----------------------------------------------------------------------------//
let validSubTargets = HasV60SubT in
}
-// Return true if a given MI can accomodate given offset.
+// Return true if a given MI can accommodate given offset.
// Use abs estimate as oppose to the exact number.
// TODO: This will need to be changed to use MC level
// definition of instruction extendable field size.
}
-// Inserts branching instructions in reverse order of their occurence.
+// Inserts branching instructions in reverse order of their occurrence.
// e.g. jump_t t1 (i1)
// jump t2 (i2)
// Jumpers = {i2, i1}
defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
-// Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
+// Compiler would want to generate 'zxtb' instead of 'and' because 'zxtb' has
// predicated forms while 'and' doesn't. Since integrated assembler can't
// handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
// immediate operand is set to '255'.
// MemAccessSize is represented as 1+log2(N) where N is size in bits.
enum class MemAccessSize {
- NoMemAccess = 0, // Not a memory acces instruction.
+ NoMemAccess = 0, // Not a memory access instruction.
ByteAccess = 1, // Byte access instruction (memb).
HalfWordAccess = 2, // Half word access instruction (memh).
WordAccess = 3, // Word access instruction (memw).
AccumulatorPos = 54,
AccumulatorMask = 0x1,
- // Complex XU, prevent xu competition by prefering slot3
+ // Complex XU, prevent xu competition by preferring slot3
PrefersSlot3Pos = 55,
PrefersSlot3Mask = 0x1,
k = j + distance;
(j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) {
- // Check if reversable.
+ // Check if reversible.
bool bisReversable = true;
if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) &&
isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) {