--- /dev/null
+/*\r
+ Produced by NSL Core(version=20101103), IP ARCH, Inc. Wed Aug 10 18:37:57 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
+*/\r
+#include <systemc.h>\r
+#include "spi_controler.sc"\r
+#include <stdlib.h>\r
+sc_clock m_clock("m_clock",10,0.5,0,false);\r
+sc_signal<bool> p_reset;\r
+sc_signal<sc_uinit<8> > send_data;\r
+sc_signal<sc_uinit<8> > resv_data;\r
+sc_signal<sc_uint<1> > send;\r
+sc_signal<sc_uint<1> > read_MOSI;\r
+sc_signal<sc_uint<1> > write_MOSO;\r
+\r
+spi_controler spi_controler("spi_controler");\r
+\r
+static int ctrl_clock=0;\r
+SC_MODULE (c_clock) {\r
+ sc_in<bool> m_clock;\r
+ void do_reset() {\r
+ ctrl_clock++;\r
+ if(ctrl_clock==0) p_reset=1;\r
+ if(ctrl_clock==1) p_reset=0\r
+ }\r
+ SC_CTOR(c_clock) {\r
+ SC_METHOD(do_reset);\r
+ sensitive << m_clock.pos();\r
+ }\r
+};\r
+\r
+int sc_main(int argc, char *argv[])\r
+{\r
+ int stop;\r
+ if(argc>1 && (stop=atoi(argv[1])<=0)) stop=1000;\r
+ sc_trace_file *tf = sc_create_vcd_trace_file("spi_controler");\r
+ sc_trace(tf,spi_controler.p_reset,"spi_controler.p_reset");\r
+ sc_trace(tf,spi_controler.m_clock,"spi_controler.m_clock");\r
+ sc_trace(tf,spi_controler.send_data,"spi_controler.send_data");\r
+ sc_trace(tf,spi_controler.resv_data,"spi_controler.resv_data");\r
+ sc_trace(tf,spi_controler.send,"spi_controler.send");\r
+ sc_trace(tf,spi_controler.read_MOSI,"spi_controler.read_MOSI");\r
+ sc_trace(tf,spi_controler.write_MOSO,"spi_controler.write_MOSO");\r
+ c_clock cclk("cclk");\r
+ cclk.m_clock(m_clock);\r
+ spi_controler.p_reset(p_reset);\r
+ spi_controler.m_clock(m_clock);\r
+ spi_controler.send_data(send_data);\r
+ spi_controler.resv_data(resv_data);\r
+ spi_controler.send(send);\r
+ spi_controler.read_MOSI(read_MOSI);\r
+ spi_controler.write_MOSO(write_MOSO);\r
+ sc_start(stop, SC_NS);\r
+ sc_close_vcd_trace_file(tf)\r
+}\r
+/*\r
+ Produced by NSL Core(version=20101103), IP ARCH, Inc. Wed Aug 10 18:37:57 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
+*/\r
--- /dev/null
+/*\r
+ Produced by NSL Core(version=20101103), IP ARCH, Inc. Wed Aug 10 17:45:54 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
+*/\r
+\r
+\r
+`timescale 1ns / 1ps\r
+`default_nettype none\r
+\r
+\r
+//synthesis translate_off\r
+module tb;\r
+ parameter tCYC=2;\r
+ parameter tPD=(tCYC/10);\r
+\r
+ reg p_reset;\r
+ reg m_clock;\r
+ reg [7:0] send_data;\r
+ wire [7:0] resv_data;\r
+ reg send;\r
+ reg read_MOSI;\r
+ reg write_MOSO;\r
+\r
+ spi_controler spi_controler_instance(\r
+ .p_reset(p_reset),\r
+ .m_clock(m_clock),\r
+ .send_data(send_data),\r
+ .resv_data(resv_data),\r
+ .send(send),\r
+ .read_MOSI(read_MOSI),\r
+ .write_MOSO(write_MOSO)\r
+ );\r
+\r
+ initial forever #(tCYC/2) m_clock = ~m_clock;\r
+\r
+ initial begin\r
+ $dumpfile("spi_controler.vcd");\r
+ $dumpvars(0,spi_controler_instance);\r
+ end\r
+\r
+ initial begin\r
+ #(tPD)\r
+ p_reset = 1;\r
+ m_clock = 0;\r
+ #(tCYC)\r
+ p_reset = 0;\r
+ end\r
+\r
+endmodule\r
+\r
+//synthesis translate_on\r