qemu_irq *cpu_exit_irq;
int via_devfn;
PCIBus *pci_bus;
- ISADevice *isa_dev;
uint8_t *eeprom_buf;
i2c_bus *smbus;
int i;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DeviceState *eeprom;
- ISADevice *rtc_state;
CPUState *env;
/* init CPUs */
DMA_init(0, cpu_exit_irq);
/* Super I/O */
- isa_dev = isa_create_simple("i8042");
+ isa_create_simple("i8042");
- rtc_state = rtc_init(2000, NULL);
+ rtc_init(2000, NULL);
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
target_long bios_size;
int64_t kernel_entry;
PCIBus *pci_bus;
- ISADevice *isa_dev;
CPUState *env;
- ISADevice *rtc_state;
- FDCtrl *floppy_controller;
- MaltaFPGAState *malta_fpga;
qemu_irq *i8259;
qemu_irq *cpu_exit_irq;
int piix4_devfn;
be = 0;
#endif
/* FPGA */
- malta_fpga = malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
+ malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
if (kernel_filename) {
DMA_init(0, cpu_exit_irq);
/* Super I/O */
- isa_dev = isa_create_simple("i8042");
-
- rtc_state = rtc_init(2000, NULL);
+ isa_create_simple("i8042");
+
+ rtc_init(2000, NULL);
serial_isa_init(0, serial_hds[0]);
serial_isa_init(1, serial_hds[1]);
if (parallel_hds[0])
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
- floppy_controller = fdctrl_init_isa(fd);
+ fdctrl_init_isa(fd);
/* Sound card */
audio_init(pci_bus);
int bios_size;
CPUState *env;
ResetData *reset_info;
- ISADevice *rtc_state;
int i;
qemu_irq *i8259;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
isa_bus_new(NULL);
isa_bus_irqs(i8259);
- rtc_state = rtc_init(2000, NULL);
+ rtc_init(2000, NULL);
/* Register 64 KB of ISA IO space at 0x14000000 */
#ifdef TARGET_WORDS_BIGENDIAN
const char *cpu_model)
{
char *filename;
- CPUPPCState *env;
qemu_irq *pic;
ram_addr_t bios_offset;
target_phys_addr_t ram_bases[2], ram_sizes[2];
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
- kernel_filename == NULL ? 0 : 1);
+ ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
+ kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
printf("%s: register BIOS\n", __func__);
static uint32_t dcr_read_dma (void *opaque, int dcrn)
{
- ppc405_dma_t *dma;
-
- dma = opaque;
-
return 0;
}
static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
{
- ppc405_dma_t *dma;
-
- dma = opaque;
}
static void ppc405_dma_reset (void *opaque)
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
static void ppc405_gpio_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
static void ppc405_gpio_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
static void ppc405_gpio_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
static void ppc405_gpio_reset (void *opaque)
{
- ppc405_gpio_t *gpio;
-
- gpio = opaque;
}
static void ppc405_gpio_init(target_phys_addr_t base)
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *env = NULL, *envs[MAX_CPUS];
+ CPUState *env = NULL;
char *filename;
qemu_irq *pic, **openpic_irqs;
int unin_memory;
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
- envs[i] = env;
}
/* allocate RAM */
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *env = NULL, *envs[MAX_CPUS];
+ CPUState *env = NULL;
char *filename;
qemu_irq *pic, **heathrow_irqs;
int linux_boot, i;
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL);
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
- envs[i] = env;
}
/* allocate RAM */
const char *initrd_filename,
const char *cpu_model)
{
- CPUState *env = NULL, *envs[MAX_CPUS];
+ CPUState *env = NULL;
char *filename;
nvram_t nvram;
M48t59State *m48t59;
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
}
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
- envs[i] = env;
}
/* allocate RAM */
int i=0;
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
qemu_irq *irqs, *mpic, *pci_irqs;
- SerialState * serial[2];
/* Setup CPU */
env = cpu_ppc_init("e500v2_v30");
/* Serial */
if (serial_hds[0]) {
- serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
- 0, mpic[12+26], 399193,
- serial_hds[0], 1, 1);
+ serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
+ 0, mpic[12+26], 399193,
+ serial_hds[0], 1, 1);
}
if (serial_hds[1]) {
- serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
- 0, mpic[12+26], 399193,
- serial_hds[0], 1, 1);
+ serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
+ 0, mpic[12+26], 399193,
+ serial_hds[0], 1, 1);
}
/* PCI */
static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s)
{
int i;
- int w_display;
uint16_t *data_buffer;
uint8_t *data_display;
data_buffer = s->vram_ptr;
- w_display = s->scr_width * BITS / 8;
data_display = ds_get_data(s->ds);
for(i = 0; i < s->scr_height; i++) {
#if (BITS == 16)
uint32_t sysclk)
{
CPUState *env;
- qemu_irq *pic;
qemu_irq *irqs;
env = cpu_init(cpu_model);
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
- pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
+ ppcuic_init(env, irqs, 0x0C0, 0, 1);
return env;
}
if (kernel_filename) {
uint64_t entry, low, high;
- uint32_t base32;
target_phys_addr_t boot_offset;
/* Boots a kernel elf binary. */
kernel_size = load_elf(kernel_filename, NULL, NULL,
&entry, &low, &high, 1, ELF_MACHINE, 0);
- base32 = entry;
boot_info.bootstrap_pc = entry & 0x00ffffff;
if (kernel_size < 0) {
int i;
struct audsettings in_fmt;
struct audsettings out_fmt;
- struct audsettings monoout_fmt;
wm8750_out_flush(s);
out_fmt.nchannels = 2;
out_fmt.freq = s->dac_hz;
out_fmt.fmt = AUD_FMT_S16;
- monoout_fmt.endianness = 0;
- monoout_fmt.nchannels = 1;
- monoout_fmt.freq = s->rate->dac_hz;
- monoout_fmt.fmt = AUD_FMT_S16;
s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0],
CODEC ".speaker", s, wm8750_audio_out_cb, &out_fmt);
} version;
DWORD version_len;
DWORD idThread;
- HANDLE hThread;
if (prefered_name != NULL)
snprintf(name_buffer, sizeof(name_buffer), "%s", prefered_name);
*phandle = &tap_overlapped;
- hThread = CreateThread(NULL, 0, tap_win32_thread_entry,
- (LPVOID)&tap_overlapped, 0, &idThread);
+ CreateThread(NULL, 0, tap_win32_thread_entry,
+ (LPVOID)&tap_overlapped, 0, &idThread);
return 0;
}
while (qemu_peek_byte(f) == QEMU_VM_SUBSECTION) {
char idstr[256];
int ret;
- uint8_t version_id, subsection, len;
+ uint8_t version_id, len;
const VMStateDescription *sub_vmsd;
- subsection = qemu_get_byte(f);
+ qemu_get_byte(f); /* subsection */
len = qemu_get_byte(f);
qemu_get_buffer(f, (uint8_t *)idstr, len);
idstr[len] = 0;