r600: check if textures are actually enabled before submission

noticed by taiu on IRC.

diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index f1fefd8..7d7e77d 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -69,7 +69,7 @@ void r600UpdateTextureState(GLcontext * ctx)
        for (unit = 0; unit < R700_MAX_TEXTURE_UNITS; unit++) {
                texUnit = &ctx->Texture.Unit[unit];
                t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
-
+               r700->textures[unit] = NULL;
                if (texUnit->_ReallyEnabled) {
                        if (!t)
                                continue;

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 37bff56..312cacf 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -52,38 +52,40 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
        radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 
        for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
-               radeonTexObj *t = r700->textures[i];
-               if (t) {
-                       if (!t->image_override)
-                               bo = t->mt->bo;
-                       else
-                               bo = t->bo;
-                       if (bo) {
-
-                               r700SyncSurf(context, bo,
-                                            RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
-                                            0, TC_ACTION_ENA_bit);
-
-                               BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
-                               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
-                               R600_OUT_BATCH(i * 7);
-                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
-                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
-                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
-                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
-                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
-                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
-                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
-                               R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
-                                                    bo,
-                                                    0,
-                                                    RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-                               R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
-                                                    bo,
-                                                    r700->textures[i]->SQ_TEX_RESOURCE3,
-                                                    RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-                               END_BATCH();
-                               COMMIT_BATCH();
+               if (ctx->Texture.Unit[i]._ReallyEnabled) {
+                       radeonTexObj *t = r700->textures[i];
+                       if (t) {
+                               if (!t->image_override)
+                                       bo = t->mt->bo;
+                               else
+                                       bo = t->bo;
+                               if (bo) {
+
+                                       r700SyncSurf(context, bo,
+                                                    RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
+                                                    0, TC_ACTION_ENA_bit);
+
+                                       BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
+                                       R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+                                       R600_OUT_BATCH(i * 7);
+                                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
+                                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
+                                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
+                                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
+                                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
+                                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
+                                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
+                                       R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
+                                                            bo,
+                                                            0,
+                                                            RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+                                       R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
+                                                            bo,
+                                                            r700->textures[i]->SQ_TEX_RESOURCE3,
+                                                            RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+                                       END_BATCH();
+                                       COMMIT_BATCH();
+                               }
                        }
                }
        }
@@ -98,16 +100,18 @@ static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *at
        radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 
        for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
-               radeonTexObj *t = r700->textures[i];
-               if (t) {
-                       BEGIN_BATCH_NO_AUTOSTATE(5);
-                       R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
-                       R600_OUT_BATCH(i * 3);
-                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
-                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
-                       R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
-                       END_BATCH();
-                       COMMIT_BATCH();
+               if (ctx->Texture.Unit[i]._ReallyEnabled) {
+                       radeonTexObj *t = r700->textures[i];
+                       if (t) {
+                               BEGIN_BATCH_NO_AUTOSTATE(5);
+                               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
+                               R600_OUT_BATCH(i * 3);
+                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
+                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
+                               R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
+                               END_BATCH();
+                               COMMIT_BATCH();
+                       }
                }
        }
 }
@@ -121,16 +125,18 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom
        radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 
        for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
-               radeonTexObj *t = r700->textures[i];
-               if (t) {
-                       BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
-                       R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
-                       R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
-                       R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
-                       R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
-                       R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
-                       END_BATCH();
-                       COMMIT_BATCH();
+               if (ctx->Texture.Unit[i]._ReallyEnabled) {
+                       radeonTexObj *t = r700->textures[i];
+                       if (t) {
+                               BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
+                               R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
+                               R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
+                               R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
+                               R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
+                               R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
+                               END_BATCH();
+                               COMMIT_BATCH();
+                       }
                }
        }
 }
@@ -1176,9 +1182,11 @@ static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom)
        R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
        for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
-               radeonTexObj *t = r700->textures[i];
-               if (t)
-                       count++;
+               if (ctx->Texture.Unit[i]._ReallyEnabled) {
+                       radeonTexObj *t = r700->textures[i];
+                       if (t)
+                               count++;
+               }
        }
        radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
        return count * 31;