Add vstr{s,d} to the integrated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1603893003 .

diff --git a/src/DartARM32/assembler_arm.cc b/src/DartARM32/assembler_arm.cc
index 6b0bfde..d62aa29 100644 (file)
--- a/src/DartARM32/assembler_arm.cc
+++ b/src/DartARM32/assembler_arm.cc
@@ -757,8 +757,8 @@ void Assembler::vldrs(SRegister sd, Address ad, Condition cond) {
                      B11 | B9 | ad.vencoding();
   Emit(encoding);
 }
-#endif
 
+// Moved to Arm32::AssemblerARM32::vstrs()
 void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
@@ -772,8 +772,6 @@ void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
   Emit(encoding);
 }
 
-#if 0
-// Moved to ARM32::AssemblerARM32::vldrd()
 void Assembler::vldrd(DRegister dd, Address ad, Condition cond) {
   ASSERT(TargetCPUFeatures::vfp_supported());
   ASSERT(dd != kNoDRegister);

diff --git a/src/DartARM32/assembler_arm.h b/src/DartARM32/assembler_arm.h
index 4de9e66..93e91af 100644 (file)
--- a/src/DartARM32/assembler_arm.h
+++ b/src/DartARM32/assembler_arm.h
@@ -635,13 +635,15 @@ class Assembler : public ValueObject {
 #if 0
   // Moved to ARM32::AssemblerARM32::vldrs()
   void vldrs(SRegister sd, Address ad, Condition cond = AL);
-#endif
+  // Moved to Arm32::AssemblerARM32::vstrs()
   void vstrs(SRegister sd, Address ad, Condition cond = AL);
-#if 0
+#endif
   // Moved to ARM32::AssemblerARM32::vldrd()
   void vldrd(DRegister dd, Address ad, Condition cond = AL);
-#endif
+#if 0
+  // Moved to Arm32::AssemblerARM32::vstrd()
   void vstrd(DRegister dd, Address ad, Condition cond = AL);
+#endif
 
   void vldms(BlockAddressMode am, Register base,
              SRegister first, SRegister last, Condition cond = AL);

diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index a055b92..fdb2686 100644 (file)
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2262,6 +2262,47 @@ void AssemblerARM32::vmuld(const Operand *OpDd, const Operand *OpDn,
   emitVFPddd(Cond, VmuldOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress,
+                           CondARM32::Cond Cond, const TargetInfo &TInfo) {
+  // VSTR - ARM section A8.8.413, encoding A1:
+  //   vstr<c> <Dd>, [<Rn>{, #+/-<imm>}]
+  //
+  // cccc1101UD00nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
+  // iiiiiiii=abs(Opcode), and U=1 if Opcode>=0,
+  constexpr const char *Vstrd = "vstrd";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vstrd);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Address;
+  if (encodeAddress(OpAddress, Address, TInfo) != EncodedAsImmRegOffset)
+    assert(false);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
+                     (encodeCondition(Cond) << kConditionShift) |
+                     (getYInRegYXXXX(Dd) << 22) |
+                     (getXXXXInRegYXXXX(Dd) << 12) | Address;
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::vstrs(const Operand *OpSd, const Operand *OpAddress,
+                           CondARM32::Cond Cond, const TargetInfo &TInfo) {
+  // VSTR - ARM section A8.8.413, encoding A2:
+  //   vstr<c> <Sd>, [<Rn>{, #+/-<imm>]]
+  //
+  // cccc1101UD01nnnndddd1010iiiiiiii where cccc=Cond, nnnn=Rn, ddddD=Sd,
+  // iiiiiiii=abs(Opcode), and U=1 if Opcode >= 0;
+  constexpr const char *Vstrs = "vstrs";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vstrs);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Address;
+  if (encodeAddress(OpAddress, Address, TInfo) != EncodedAsImmRegOffset)
+    assert(false);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding =
+      B27 | B26 | B24 | B11 | B9 | (encodeCondition(Cond) << kConditionShift) |
+      (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sd) << 12) | Address;
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VSUB (floating-point) - ARM section A8.8.415, encoding A2:

diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index 4b59a02..953b95b 100644 (file)
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -368,6 +368,24 @@ public:
   void vpush(const Variable *OpBaseReg, SizeT NumConsecRegs,
              CondARM32::Cond Cond);
 
+  void vstrd(const Operand *OpDd, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetInfo &TInfo);
+
+  void vstrd(const Operand *OpDd, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetLowering *Lowering) {
+    const TargetInfo TInfo(Lowering);
+    vstrd(OpDd, OpAddress, Cond, TInfo);
+  }
+
+  void vstrs(const Operand *OpSd, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetInfo &TInfo);
+
+  void vstrs(const Operand *OpSd, const Operand *OpAddress,
+             CondARM32::Cond Cond, const TargetLowering *Lowering) {
+    const TargetInfo TInfo(Lowering);
+    vstrs(OpSd, OpAddress, Cond, TInfo);
+  }
+
   void vsubd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 

diff --git a/src/IceInstARM32.cpp b/src/IceInstARM32.cpp
index a06d71d..a82c148 100644 (file)
--- a/src/IceInstARM32.cpp
+++ b/src/IceInstARM32.cpp
@@ -1668,7 +1668,12 @@ void InstARM32Str::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   Type Ty = getSrc(0)->getType();
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
-  if (isVectorType(Ty) || isScalarFloatingType(Ty))
+  if (isScalarFloatingType(Ty)) {
+    if (Ty == IceType_f32)
+      Asm->vstrs(getSrc(0), getSrc(1), getPredicate(), Func->getTarget());
+    else
+      Asm->vstrd(getSrc(0), getSrc(1), getPredicate(), Func->getTarget());
+  } else if (isVectorType(Ty))
     // TODO(kschimpf) Handle case.
     Asm->setNeedsTextFixup();
   else

diff --git a/tests_lit/assembler/arm32/vstr.ll b/tests_lit/assembler/arm32/vstr.ll
new file mode 100644 (file)
index 0000000..df6f397
--- /dev/null
+++ b/tests_lit/assembler/arm32/vstr.ll
@@ -0,0 +1,61 @@
+; Show that we know how to translate (floating point) vstr.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   -reg-use r5,r6,s20,d20 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   -reg-use r5,r6,s20,d20 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   -reg-use r5,r6,s20,d20 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   -reg-use r5,r6,s20,d20 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+define internal void @testFloat() {
+; ASM-LABEL: testFloat:
+; DIS-LABEL: 00000000 <testFloat>:
+; IASM-LABEL: testFloat:
+
+entry:
+; ASM: .LtestFloat$entry:
+
+  %vaddr = inttoptr i32 0 to float*
+  store float 0.0, float* %vaddr, align 1
+
+; ASM:  vstr    s20, [r5]
+; DIS:  14:     ed96aa00
+; IASM-NOT: vstr
+
+  ret void
+}
+
+define internal void @testDouble() {
+; ASM-LABEL: testDouble:
+; DIS-LABEL: 00000030 <testDouble>:
+; IASM-LABEL: testDouble:
+
+entry:
+; ASM: .LtestDouble$entry:
+
+  %vaddr = inttoptr i32 0 to double*
+  store double 0.0, double* %vaddr, align 1
+
+; ASM:  vstr    d20, [r5]
+; DIS:  3c:     edc54b00
+; IASM-NOT: vstr
+
+  ret void
+}