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[X86][AVX512] Tag CLWB instruction to CLFLUSH/PREFETCH scheduler class
author
Simon Pilgrim
<llvm-dev@redking.me.uk>
Fri, 8 Dec 2017 15:19:10 +0000
(15:19 +0000)
committer
Simon Pilgrim
<llvm-dev@redking.me.uk>
Fri, 8 Dec 2017 15:19:10 +0000
(15:19 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320156
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/X86/X86InstrInfo.td
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diff --git
a/lib/Target/X86/X86InstrInfo.td
b/lib/Target/X86/X86InstrInfo.td
index
1a495bf
..
eed129a
100644
(file)
--- a/
lib/Target/X86/X86InstrInfo.td
+++ b/
lib/Target/X86/X86InstrInfo.td
@@
-2723,10
+2723,9
@@
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
IIC_SSE_PREFETCH>, PD;
-let Predicates = [HasCLWB] in
+let Predicates = [HasCLWB]
, SchedRW = [WriteLoad]
in
def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
- [(int_x86_clwb addr:$src)]>, PD;
-
+ [(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD;
//===----------------------------------------------------------------------===//
// Subsystems.