sprite is enabled.(1st sprite is broken tho...)

diff --git a/tools/qt_proj_test5/ppu.vhd b/tools/qt_proj_test5/ppu.vhd
index 5021ef1..53e6cec 100644 (file)
--- a/tools/qt_proj_test5/ppu.vhd
+++ b/tools/qt_proj_test5/ppu.vhd
@@ -16,6 +16,12 @@ entity ppu is
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);
     signal dbg_plt_addr                     : out std_logic_vector (4 downto 0);
     signal dbg_plt_data                     : out std_logic_vector (7 downto 0);
+    signal dbg_p_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);
+    signal dbg_p_oam_addr                   : out std_logic_vector (7 downto 0);
+    signal dbg_p_oam_data                   : out std_logic_vector (7 downto 0);
+    signal dbg_s_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);
+    signal dbg_s_oam_addr                   : out std_logic_vector (4 downto 0);
+    signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);
 
     signal dbg_ppu_addr_we_n                : out std_logic;
     signal dbg_ppu_clk_cnt                  : out std_logic_vector(1 downto 0);
@@ -57,6 +63,12 @@ component ppu_render
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);
     signal dbg_plt_addr                     : out std_logic_vector (4 downto 0);
     signal dbg_plt_data                     : out std_logic_vector (7 downto 0);
+    signal dbg_p_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);
+    signal dbg_p_oam_addr                   : out std_logic_vector (7 downto 0);
+    signal dbg_p_oam_data                   : out std_logic_vector (7 downto 0);
+    signal dbg_s_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);
+    signal dbg_s_oam_addr                   : out std_logic_vector (4 downto 0);
+    signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);
     
     
             clk         : in std_logic;
@@ -203,6 +215,12 @@ begin
     dbg_disp_nt, dbg_disp_attr, dbg_disp_ptn_h, dbg_disp_ptn_l,
     dbg_plt_addr                     ,
     dbg_plt_data                     ,
+    dbg_p_oam_ce_rn_wn              ,
+    dbg_p_oam_addr                  ,
+    dbg_p_oam_data                  ,
+    dbg_s_oam_ce_rn_wn              ,
+    dbg_s_oam_addr                  ,
+    dbg_s_oam_data                  ,
     
             clk, vga_clk, mem_clk, rst_n,
             rd_n, wr_n, ale, vram_ad, vram_a,

diff --git a/tools/qt_proj_test5/qt_proj_test5.vhd b/tools/qt_proj_test5/qt_proj_test5.vhd
index 0093df0..3b0b321 100644 (file)
--- a/tools/qt_proj_test5/qt_proj_test5.vhd
+++ b/tools/qt_proj_test5/qt_proj_test5.vhd
@@ -74,6 +74,12 @@ architecture rtl of qt_proj_test5 is
         signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);\r
         signal dbg_plt_addr                     : out std_logic_vector (4 downto 0);\r
         signal dbg_plt_data                     : out std_logic_vector (7 downto 0);\r
+        signal dbg_p_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);\r
+        signal dbg_p_oam_addr                   : out std_logic_vector (7 downto 0);\r
+        signal dbg_p_oam_data                   : out std_logic_vector (7 downto 0);\r
+        signal dbg_s_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);\r
+        signal dbg_s_oam_addr                   : out std_logic_vector (4 downto 0);\r
+        signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);\r
 \r
         signal dbg_ppu_addr_we_n                : out std_logic;\r
         signal dbg_ppu_clk_cnt                  : out std_logic_vector(1 downto 0);\r
@@ -182,9 +188,17 @@ architecture rtl of qt_proj_test5 is
     signal dbg_vga_x                        : std_logic_vector (9 downto 0);\r
     signal dbg_plt_addr                     : std_logic_vector (4 downto 0);\r
     signal dbg_plt_data                     : std_logic_vector (7 downto 0);\r
+    signal dbg_p_oam_ce_rn_wn               : std_logic_vector (2 downto 0);\r
+    signal dbg_p_oam_addr                   : std_logic_vector (7 downto 0);\r
+    signal dbg_p_oam_data                   : std_logic_vector (7 downto 0);\r
+    signal dbg_s_oam_ce_rn_wn               : std_logic_vector (2 downto 0);\r
+    signal dbg_s_oam_addr                   : std_logic_vector (4 downto 0);\r
+    signal dbg_s_oam_data                   : std_logic_vector (7 downto 0);\r
     signal dbg_ppu_data_dummy               : std_logic_vector (7 downto 0);\r
     signal dbg_ppu_status_dummy             : std_logic_vector (7 downto 0);\r
     signal dbg_ppu_scrl_x_dummy             : std_logic_vector (7 downto 0);\r
+    signal dbg_ppu_scrl_y_dummy             : std_logic_vector (7 downto 0);\r
+    signal dbg_disp_ptn_h_dummy, dbg_disp_ptn_l_dummy   : std_logic_vector (15 downto 0);\r
     \r
     \r
 \r
@@ -204,20 +218,29 @@ begin
     dbg_ppu_scrl_x(2) <= wr_n;\r
     dbg_ppu_scrl_x(3) <= nt0_ce_n;\r
     dbg_ppu_scrl_x(4) <= vga_clk_n;\r
+    dbg_ppu_scrl_y(2 downto 0) <= dbg_p_oam_ce_rn_wn(2 downto 0);\r
+    dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;\r
+    dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;\r
     \r
     ppu_inst: ppu port map (  \r
         dbg_ppu_ce_n                                        ,\r
         dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status_dummy          ,\r
         dbg_ppu_addr_dummy                                        ,\r
-        dbg_ppu_data_dummy, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y        ,\r
+        dbg_ppu_data_dummy, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y_dummy        ,\r
 \r
         dbg_ppu_clk                      ,\r
         dbg_nes_x                        ,\r
         dbg_vga_x                        ,\r
         dbg_disp_nt, dbg_disp_attr                          ,\r
-        dbg_disp_ptn_h, dbg_disp_ptn_l                      ,\r
+        dbg_disp_ptn_h, dbg_disp_ptn_l_dummy                      ,\r
         dbg_plt_addr                     ,\r
         dbg_plt_data                     ,\r
+        dbg_p_oam_ce_rn_wn              ,\r
+        dbg_p_oam_addr                  ,\r
+        dbg_p_oam_data                  ,\r
+        dbg_s_oam_ce_rn_wn              ,\r
+        dbg_s_oam_addr                  ,\r
+        dbg_s_oam_data                  ,\r
         dbg_ppu_addr_we_n                                   ,\r
         dbg_ppu_clk_cnt                                     ,\r
 \r
@@ -306,7 +329,7 @@ end;
             init_step_cnt := 0;\r
             plt_step_cnt := 0;\r
             nt_step_cnt := 0;\r
-                               spr_step_cnt := 0;\r
+            spr_step_cnt := 0;\r
             enable_ppu_step_cnt := 0;\r
 \r
         elsif (rising_edge(cpu_clk)) then\r
@@ -349,7 +372,7 @@ end;
                         ppu_set(16#2006#, 16#00#);\r
                     \r
                     elsif (plt_step_cnt = 4) then\r
-                        --set palette data\r
+                        --set palette bg data\r
                         ppu_set(16#2007#, 16#11#);\r
                     elsif (plt_step_cnt = 6) then\r
                         ppu_set(16#2007#, 16#01#);\r
@@ -384,10 +407,38 @@ end;
                         ppu_set(16#2007#, 16#1c#);\r
                     elsif (plt_step_cnt = 34) then\r
                         ppu_set(16#2007#, 16#2c#);\r
- \r
+\r
+                     elsif (plt_step_cnt = 36) then\r
+                        --below is sprite pallete\r
+                        ppu_set(16#2007#, 16#00#);\r
+                    elsif (plt_step_cnt = 38) then\r
+                        ppu_set(16#2007#, 16#24#);\r
+                    elsif (plt_step_cnt = 40) then\r
+                        ppu_set(16#2007#, 16#1b#);\r
+                    elsif (plt_step_cnt = 42) then\r
+                        ppu_set(16#2007#, 16#11#);\r
+\r
+                    elsif (plt_step_cnt = 44) then\r
+                        ppu_set(16#2007#, 16#00#);\r
+                    elsif (plt_step_cnt = 46) then\r
+                        ppu_set(16#2007#, 16#32#);\r
+                    elsif (plt_step_cnt = 48) then\r
+                        ppu_set(16#2007#, 16#16#);\r
+                    elsif (plt_step_cnt = 50) then\r
+                        ppu_set(16#2007#, 16#20#);\r
+\r
+                    elsif (plt_step_cnt = 52) then\r
+                        ppu_set(16#2007#, 16#00#);\r
+                    elsif (plt_step_cnt = 54) then\r
+                        ppu_set(16#2007#, 16#26#);\r
+                    elsif (plt_step_cnt = 56) then\r
+                        ppu_set(16#2007#, 16#01#);\r
+                    elsif (plt_step_cnt = 58) then\r
+                        ppu_set(16#2007#, 16#31#);\r
+\r
                     else\r
                         ppu_clr;\r
-                        if (plt_step_cnt > 10) then\r
+                        if (plt_step_cnt > 58) then\r
                             global_step_cnt := global_step_cnt + 1;\r
                         end if;\r
                     end if;\r
@@ -396,7 +447,7 @@ end;
                 elsif (global_step_cnt = 2) then\r
                     --step1 = name table set.\r
                     if (nt_step_cnt = 0) then\r
-                        --set vram addr 2006 (first row, 6th col)\r
+                        --set vram addr 2005 (first row, 6th col)\r
                         ppu_set(16#2006#, 16#20#);\r
                     elsif (nt_step_cnt = 2) then\r
                         ppu_set(16#2006#, 16#06#);\r
@@ -435,7 +486,7 @@ end;
                         ppu_set(16#2007#, 16#21#);\r
 \r
                     elsif (nt_step_cnt = 32) then\r
-                        --set vram addr 23c1\r
+                        --set vram addr 23c1 (attribute)\r
                         ppu_set(16#2006#, 16#23#);\r
                     elsif (nt_step_cnt = 34) then\r
                         ppu_set(16#2006#, 16#c1#);\r
@@ -451,32 +502,72 @@ end;
                     end if;\r
                     nt_step_cnt := nt_step_cnt + 1;\r
                     \r
-                elsif (global_step_cnt = 2) then\r
+                elsif (global_step_cnt = 3) then\r
                     --step2 = sprite set.\r
                     if (spr_step_cnt = 0) then\r
-                        --set sprite addr=00\r
+                        --set sprite addr=00 (first sprite)\r
                         ppu_set(16#2003#, 16#00#);\r
                     elsif (spr_step_cnt = 2) then\r
-                        --set sprite data: y=01\r
-                        ppu_set(16#2004#, 16#01#);\r
+                        --set sprite data: y=02\r
+                        ppu_set(16#2004#, 16#02#);\r
                     elsif (spr_step_cnt = 4) then\r
                         --tile=0x4d (ascii 'M')\r
                         ppu_set(16#2004#, 16#4d#);\r
                     elsif (spr_step_cnt = 6) then\r
-                        --set sprite attr=00\r
-                        ppu_set(16#2004#, 16#00#);\r
+                        --set sprite attr=03 (palette 03)\r
+                        ppu_set(16#2004#, 16#03#);\r
                     elsif (spr_step_cnt = 8) then\r
-                        --set sprite data: x=39\r
-                        ppu_set(16#2004#, 16#27#);\r
+                        --set sprite data: x=100\r
+                        ppu_set(16#2004#, 16#64#);\r
+\r
+                    elsif (spr_step_cnt = 10) then\r
+                        --set sprite data: y=50\r
+                        ppu_set(16#2004#, 16#32#);\r
+                    elsif (spr_step_cnt = 12) then\r
+                        --tile=0x4d (ascii 'O')\r
+                        ppu_set(16#2004#, 16#4f#);\r
+                    elsif (spr_step_cnt = 14) then\r
+                        --set sprite attr=01\r
+                        ppu_set(16#2004#, 16#01#);\r
+                    elsif (spr_step_cnt = 16) then\r
+                        --set sprite data: x=30\r
+                        ppu_set(16#2004#, 16#1e#);\r
+\r
+                    elsif (spr_step_cnt = 18) then\r
+                        --set sprite data: y=53\r
+                        ppu_set(16#2004#, 16#33#);\r
+                    elsif (spr_step_cnt = 20) then\r
+                        --tile=0x4d (ascii 'P')\r
+                        ppu_set(16#2004#, 16#50#);\r
+                    elsif (spr_step_cnt = 22) then\r
+                        --set sprite attr=01\r
+                        ppu_set(16#2004#, 16#01#);\r
+                    elsif (spr_step_cnt = 24) then\r
+                        --set sprite data: x=33\r
+                        ppu_set(16#2004#, 16#21#);\r
+\r
+                    elsif (spr_step_cnt = 26) then\r
+                        --set sprite data: y=61\r
+                        ppu_set(16#2004#, 16#3d#);\r
+                    elsif (spr_step_cnt = 28) then\r
+                        --tile=0x4d (ascii 'Q')\r
+                        ppu_set(16#2004#, 16#50#);\r
+                    elsif (spr_step_cnt = 30) then\r
+                        --set sprite attr=02\r
+                        ppu_set(16#2004#, 16#02#);\r
+                    elsif (spr_step_cnt = 32) then\r
+                        --set sprite data: x=35\r
+                        ppu_set(16#2004#, 16#23#);\r
+\r
                     else\r
                         ppu_clr;\r
-                        if (spr_step_cnt > 8) then\r
+                        if (spr_step_cnt > 32) then\r
                             global_step_cnt := global_step_cnt + 1;\r
                         end if;\r
                     end if;\r
                     spr_step_cnt := spr_step_cnt + 1;\r
 \r
-                elsif (global_step_cnt = 3) then\r
+                elsif (global_step_cnt = 4) then\r
                     --final step = enable ppu.\r
                     if (enable_ppu_step_cnt = 0) then\r
                         --show bg\r
@@ -484,7 +575,7 @@ end;
                         --PPUMASK=0e (show bg only)\r
                         ppu_set(16#2001#, 16#1e#);\r
                     elsif (enable_ppu_step_cnt = 2) then\r
-                        --show enable nmi\r
+                        --enable nmi\r
                         --PPUCTRL=80\r
                         ppu_set(16#2000#, 16#80#);\r
                     else\r

diff --git a/tools/qt_proj_test5/render.vhd b/tools/qt_proj_test5/render.vhd
index 969f207..151debe 100644 (file)
--- a/tools/qt_proj_test5/render.vhd
+++ b/tools/qt_proj_test5/render.vhd
@@ -12,6 +12,12 @@ entity ppu_render is
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);
     signal dbg_plt_addr                     : out std_logic_vector (4 downto 0);
     signal dbg_plt_data                     : out std_logic_vector (7 downto 0);
+    signal dbg_p_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);
+    signal dbg_p_oam_addr                   : out std_logic_vector (7 downto 0);
+    signal dbg_p_oam_data                   : out std_logic_vector (7 downto 0);
+    signal dbg_s_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);
+    signal dbg_s_oam_addr                   : out std_logic_vector (4 downto 0);
+    signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);
     
             clk         : in std_logic;
             vga_clk     : in std_logic;
@@ -75,6 +81,12 @@ component vga_ctl
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);
     signal dbg_plt_addr                     : out std_logic_vector (4 downto 0);
     signal dbg_plt_data                     : out std_logic_vector (7 downto 0);
+    signal dbg_p_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);
+    signal dbg_p_oam_addr                   : out std_logic_vector (7 downto 0);
+    signal dbg_p_oam_data                   : out std_logic_vector (7 downto 0);
+    signal dbg_s_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);
+    signal dbg_s_oam_addr                   : out std_logic_vector (4 downto 0);
+    signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);
 
             vga_clk     : in std_logic;
             mem_clk     : in std_logic;
@@ -163,6 +175,12 @@ begin
             dbg_disp_ptn_h, dbg_disp_ptn_l ,
             dbg_plt_addr                     ,
             dbg_plt_data                     ,
+            dbg_p_oam_ce_rn_wn              ,
+            dbg_p_oam_addr                  ,
+            dbg_p_oam_data                  ,
+            dbg_s_oam_ce_rn_wn              ,
+            dbg_s_oam_addr                  ,
+            dbg_s_oam_data                  ,
             vga_clk     ,
             mem_clk     ,
             rst_n       ,

diff --git a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
index d691161..9010cfc 100644 (file)
--- a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
+++ b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
@@ -14,6 +14,7 @@ vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /sim_board=qt_p
 ###add wave *\r
 \r
 #add wave  -label vga_clk sim:/testbench_qt_proj_test5/dbg_cpu_clk\r
+add wave -label vga_clk_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_x(4)\r
 add wave  -label ppu_clk sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_clk\r
 add wave  sim:/testbench_qt_proj_test5/sim_board/rst_n\r
 \r
@@ -24,15 +25,20 @@ add wave -label ppu_mask  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_
 \r
 \r
 add wave -divider vga_pos\r
-#add wave -radix decimal -unsigned  -label vga_x sim:/testbench_qt_proj_test5/sim_board/dbg_addr\r
 add wave -label nes_x           -radix decimal -unsigned  -label nes_x sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_addr\r
 add wave -label dbg_disp_nt     -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_nt\r
 add wave -label dbg_disp_attr   -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_attr\r
 add wave -label dbg_disp_ptn_h  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_h\r
-add wave -label dbg_disp_ptn_l  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_l\r
+#add wave -label dbg_disp_ptn_l  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_l\r
+\r
+add wave -divider sprite\r
+add wave -label p_oam_ce_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_y(2)\r
+add wave -label p_oam_r_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_y(1)\r
+add wave -label p_oam_w_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_y(0)\r
+add wave -label p_oam_addr  -radix hex {sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_l(7 downto 0)}\r
+add wave -label p_oam_data  -radix hex {sim:/testbench_qt_proj_test5/sim_board/dbg_disp_ptn_l (15 downto 8)}\r
 \r
 add wave -divider vram\r
-add wave -label vga_clk_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_x(4)\r
 add wave -label ale sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_x(0)\r
 add wave -label rd_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_x(1)\r
 add wave -label wr_n sim:/testbench_qt_proj_test5/sim_board/dbg_ppu_scrl_x(2)\r
@@ -53,37 +59,14 @@ add wave -label g           -radix hex sim:/testbench_qt_proj_test5/sim_board/g
 add wave -label b           -radix hex sim:/testbench_qt_proj_test5/sim_board/b\r
 \r
 \r
-#add wave  sim:/testbench_qt_proj_test5/sim_board/dbg_cpu_clk\r
-#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_addr\r
-#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d_io\r
-#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_instruction\r
-#add wave  -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_int_d_bus\r
-\r
-\r
-\r
-#add wave -divider status\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d1\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d2\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_d_out\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_ea_carry\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_carry_clr_n\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_gate_n\r
-\r
-\r
-\r
-#add wave -divider status_debug\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_status\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_dec_oe_n\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_status_val\r
-#add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/dbg_stat_we_n\r
-\r
 view structure\r
 view signals\r
 \r
 ###run 10 us\r
 run 3 us\r
 \r
-run 100 us\r
+run 50 us\r
+#run 100 us\r
 \r
 wave zoom full\r
 \r

diff --git a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_rtl_vhdl.do b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_rtl_vhdl.do
index 4570d25..3e08e13 100644 (file)
--- a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_rtl_vhdl.do
+++ b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_rtl_vhdl.do
@@ -33,31 +33,49 @@ add wave -divider ppu
 add wave  -label ppu_ctrl -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/ppu_ctrl\r
 add wave  -label ppu_mask -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/ppu_mask\r
 \r
-#add wave -divider vga_pos\r
-#add wave  -label nes_x          -radix decimal -unsigned  sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/nes_x\r
-#add wave  -label dbg_disp_nt    -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_nt\r
-#add wave  -label dbg_disp_attr  -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/disp_attr\r
-#add wave  -label dbg_disp_ptn_h -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_ptn_h\r
-#add wave  -label dbg_disp_ptn_l -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_ptn_l\r
+add wave -divider vga_pos\r
+add wave  -label nes_x          -radix decimal -unsigned  sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/nes_x\r
+add wave  -label nes_y          -radix decimal -unsigned  sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/nes_y\r
+add wave  -label dbg_disp_nt    -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_nt\r
+add wave  -label dbg_disp_attr  -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/disp_attr\r
+add wave  -label dbg_disp_ptn_h -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_ptn_h\r
+add wave  -label dbg_disp_ptn_l -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/dbg_disp_ptn_l\r
+\r
+add wave -divider sprite\r
+\r
+add wave  -label oam_bus_ce_n                sim:/testbench_qt_proj_test5/sim_board/ppu_inst/oam_bus_ce_n\r
+add wave  -label p_oam_ram_ce_n                sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/p_oam_ram_ce_n\r
+add wave  -label p_oam_r_n                sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/p_oam_r_n\r
+add wave  -label p_oam_w_n                sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/p_oam_w_n\r
+add wave  -label p_oam_addr     -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/p_oam_addr\r
+add wave  -label p_oam_data     -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/p_oam_data\r
+\r
+#add wave  -label s_oam_ram_ce_n                sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/s_oam_ram_ce_n\r
+#add wave  -label s_oam_r_n                sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/s_oam_r_n\r
+#add wave  -label s_oam_w_n                sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/s_oam_w_n\r
+#add wave  -label s_oam_addr     -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/s_oam_addr\r
+#add wave  -label s_oam_data     -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/s_oam_data\r
 \r
-add wave -divider vram\r
 \r
+add wave -divider vram\r
 add wave -label ale sim:/testbench_qt_proj_test5/sim_board/ale\r
 add wave -label rd_n sim:/testbench_qt_proj_test5/sim_board/rd_n\r
 add wave -label wr_n sim:/testbench_qt_proj_test5/sim_board/wr_n\r
 \r
 add wave  -label vram_a   -radix hex sim:/testbench_qt_proj_test5/sim_board/vram_a\r
 add wave  -label vram_ad  -radix hex sim:/testbench_qt_proj_test5/sim_board/vram_ad\r
+add wave  -label v_addr   -radix hex sim:/testbench_qt_proj_test5/sim_board/v_addr\r
 #add wave  -label plt_addr -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/plt_addr\r
 #add wave  -label plt_data -radix hex sim:/testbench_qt_proj_test5/sim_board/ppu_inst/render_inst/vga_render_inst/vga_render_inst/plt_data\r
 \r
+\r
+\r
 add wave -divider nt_ram\r
-add wave  -label ce_n   sim:/testbench_qt_proj_test5/sim_board/vram_nt0/ce_n\r
-add wave  -label oe_n   sim:/testbench_qt_proj_test5/sim_board/vram_nt0/oe_n\r
-add wave  -label we_n   sim:/testbench_qt_proj_test5/sim_board/vram_nt0/we_n\r
-add wave  -label addr   -radix hex sim:/testbench_qt_proj_test5/sim_board/vram_nt0/addr\r
-add wave  -label data   -radix hex sim:/testbench_qt_proj_test5/sim_board/vram_nt0/d_io\r
-add wave  -label v_addr   -radix hex sim:/testbench_qt_proj_test5/sim_board/v_addr\r
+#add wave  -label ce_n   sim:/testbench_qt_proj_test5/sim_board/vram_nt0/ce_n\r
+#add wave  -label oe_n   sim:/testbench_qt_proj_test5/sim_board/vram_nt0/oe_n\r
+#add wave  -label we_n   sim:/testbench_qt_proj_test5/sim_board/vram_nt0/we_n\r
+#add wave  -label addr   -radix hex sim:/testbench_qt_proj_test5/sim_board/vram_nt0/addr\r
+#add wave  -label data   -radix hex sim:/testbench_qt_proj_test5/sim_board/vram_nt0/d_io\r
 \r
 add wave -divider vga_output\r
 add wave  -label h_sync_n   sim:/testbench_qt_proj_test5/sim_board/h_sync_n\r
@@ -69,5 +87,6 @@ add wave  -label b          -radix hex sim:/testbench_qt_proj_test5/sim_board/b
 \r
 view structure\r
 view signals\r
-run 15 us\r
+run 3 us\r
+run 200 us\r
 wave zoom full\r

diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd
index 36ea10e..c7b1a7f 100644 (file)
--- a/tools/qt_proj_test5/vga.vhd
+++ b/tools/qt_proj_test5/vga.vhd
@@ -20,6 +20,12 @@ entity vga_ctl is
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);\r
     signal dbg_plt_addr                     : out std_logic_vector (4 downto 0);\r
     signal dbg_plt_data                     : out std_logic_vector (7 downto 0);\r
+    signal dbg_p_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);\r
+    signal dbg_p_oam_addr                   : out std_logic_vector (7 downto 0);\r
+    signal dbg_p_oam_data                   : out std_logic_vector (7 downto 0);\r
+    signal dbg_s_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);\r
+    signal dbg_s_oam_addr                   : out std_logic_vector (4 downto 0);\r
+    signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);\r
 \r
             vga_clk     : in std_logic;\r
             mem_clk     : in std_logic;\r
@@ -79,6 +85,12 @@ component ppu_vga_render
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);\r
     signal dbg_plt_addr                     : out std_logic_vector (4 downto 0);\r
     signal dbg_plt_data                     : out std_logic_vector (7 downto 0);\r
+    signal dbg_p_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);\r
+    signal dbg_p_oam_addr                   : out std_logic_vector (7 downto 0);\r
+    signal dbg_p_oam_data                   : out std_logic_vector (7 downto 0);\r
+    signal dbg_s_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);\r
+    signal dbg_s_oam_addr                   : out std_logic_vector (4 downto 0);\r
+    signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);\r
     \r
             clk         : in std_logic;\r
             mem_clk     : in std_logic;\r
@@ -254,6 +266,12 @@ begin
         dbg_disp_ptn_h, dbg_disp_ptn_l  ,\r
         dbg_plt_addr                    ,\r
         dbg_plt_data                    ,\r
+        dbg_p_oam_ce_rn_wn              ,\r
+        dbg_p_oam_addr                  ,\r
+        dbg_p_oam_data                  ,\r
+        dbg_s_oam_ce_rn_wn              ,\r
+        dbg_s_oam_addr                  ,\r
+        dbg_s_oam_data                  ,\r
         \r
                 emu_ppu_clk_n ,\r
                 mem_clk     ,\r
@@ -306,6 +324,12 @@ entity ppu_vga_render is
     signal dbg_disp_ptn_h, dbg_disp_ptn_l   : out std_logic_vector (15 downto 0);\r
     signal dbg_plt_addr                     : out std_logic_vector (4 downto 0);\r
     signal dbg_plt_data                     : out std_logic_vector (7 downto 0);\r
+    signal dbg_p_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);\r
+    signal dbg_p_oam_addr                   : out std_logic_vector (7 downto 0);\r
+    signal dbg_p_oam_data                   : out std_logic_vector (7 downto 0);\r
+    signal dbg_s_oam_ce_rn_wn               : out std_logic_vector (2 downto 0);\r
+    signal dbg_s_oam_addr                   : out std_logic_vector (4 downto 0);\r
+    signal dbg_s_oam_data                   : out std_logic_vector (7 downto 0);\r
     \r
             clk         : in std_logic;\r
             mem_clk     : in std_logic;\r
@@ -648,6 +672,12 @@ begin
     dbg_disp_ptn_l <= disp_ptn_l;\r
     dbg_plt_addr <= plt_addr;\r
     dbg_plt_data <= plt_data;\r
+    dbg_p_oam_ce_rn_wn               <= p_oam_ram_ce_n & p_oam_r_n & p_oam_w_n;\r
+    dbg_p_oam_addr                   <= p_oam_addr;\r
+    dbg_p_oam_data                   <= p_oam_data;\r
+    dbg_s_oam_ce_rn_wn               <= s_oam_ram_ce_n & s_oam_r_n & s_oam_w_n;\r
+    dbg_s_oam_addr                   <= s_oam_addr;\r
+    dbg_s_oam_data                   <= p_oam_data;\r
 \r
 \r
     clk_n <= not clk;\r
@@ -861,9 +891,9 @@ begin
     p_oam_w_n <= r_nw when oam_bus_ce_n = '0' else\r
                 '1';\r
     oam_d_buf_w : tri_state_buffer generic map (dsize)\r
-            port map (r_nw, oam_plt_data, p_oam_data);\r
+            port map (p_oam_w_n, oam_plt_data, p_oam_data);\r
     oam_d_buf_r : tri_state_buffer generic map (dsize)\r
-            port map (r_n, p_oam_data, oam_plt_data);\r
+            port map (p_oam_r_n, p_oam_data, oam_plt_data);\r
 \r
     p_oam_ram_ctl : ram_ctrl\r
             port map (mem_clk, p_oam_ram_ce_n_in, p_oam_r_n, p_oam_w_n, p_oam_ram_ce_n);\r
@@ -894,8 +924,8 @@ begin
 \r
     s_oam_ram_ctl : ram_ctrl\r
             port map (mem_clk, s_oam_ram_ce_n_in, s_oam_r_n, s_oam_w_n, s_oam_ram_ce_n);\r
---    secondary_oam_inst : ram generic map (5, dsize)\r
---            port map (mem_clk, s_oam_ram_ce_n, s_oam_r_n, s_oam_w_n, s_oam_addr, s_oam_data);\r
+    secondary_oam_inst : ram generic map (5, dsize)\r
+            port map (mem_clk, s_oam_ram_ce_n, s_oam_r_n, s_oam_w_n, s_oam_addr, s_oam_data);\r
 \r
     spr_y_inst : d_flip_flop generic map(dsize)\r
             port map (clk_n, p_oam_cnt_res_n, '1', spr_y_we_n, s_oam_data, spr_y_tmp);\r
@@ -1002,6 +1032,7 @@ end;
         if (rst_n = '0') then\r
             nt_we_n <= '1';\r
             ppu_status <= (others => '0');\r
+            s_oam_data <= (others => 'Z');\r
             stop_rgb;\r
         else\r
 \r