This is a temporary workaround for native arm linux builds:
PR18996: Changing regalloc order breaks "lencod" on native arm linux builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202433
91177308-0d34-0410-b5e6-
96231b3b80d8
/// (3) Bottom-up allocation is no longer guaranteed to optimally color.
virtual bool reverseLocalAssignment() const { return false; }
+ /// Allow the target to override register assignment heuristics based on the
+ /// live range size. If this returns false, then local live ranges are always
+ /// assigned in order regardless of their size. This is a temporary hook for
+ /// debugging downstream codegen failures exposed by regalloc.
+ virtual bool mayOverrideLocalAssignment() const { return true; }
+
/// requiresRegisterScavenging - returns true if the target requires (and can
/// make use of) the register scavenger.
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
// Giant live ranges fall back to the global assignment heuristic, which
// prevents excessive spilling in pathological cases.
bool ReverseLocal = TRI->reverseLocalAssignment();
- bool ForceGlobal = !ReverseLocal &&
+ bool ForceGlobal = !ReverseLocal && TRI->mayOverrideLocalAssignment() &&
(Size / SlotIndex::InstrDist) > (2 * MRI->getRegClass(Reg)->getNumRegs());
if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
.setMIFlags(MIFlags);
}
+bool ARMBaseRegisterInfo::mayOverrideLocalAssignment() const {
+ // The native linux build hits a downstream codegen bug when this is enabled.
+ return STI.isTargetDarwin();
+}
+
bool ARMBaseRegisterInfo::
requiresRegisterScavenging(const MachineFunction &MF) const {
return true;
unsigned MIFlags = MachineInstr::NoFlags)const;
/// Code Generation virtual methods...
+ virtual bool mayOverrideLocalAssignment() const;
+
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;