return &Op;
MachineInstr *Def = MRI.getVRegDef(Op.getReg());
- if (Def->isMoveImmediate()) {
+ if (Def && Def->isMoveImmediate()) {
MachineOperand &ImmSrc = Def->getOperand(1);
if (ImmSrc.isImm())
return &ImmSrc;
ret void
}
+ define amdgpu_kernel void @undefined_vreg_operand() {
+ unreachable
+ }
+
declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #0 = { nounwind }
S_ENDPGM
...
+---
+# There is only an undef use operand for %1, so there is no
+# corresponding defining instruction
+
+name: undefined_vreg_operand
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: '' }
+ - { id: 1, class: vgpr_32, preferred-register: '' }
+ - { id: 2, class: vgpr_32, preferred-register: '' }
+body: |
+ bb.0:
+ %0 = V_MOV_B32_e32 0, implicit %exec
+ %2 = V_XOR_B32_e64 killed %0, undef %1, implicit %exec
+ S_ENDPGM
+
+...