drm/i915: Compact device info access by a small re-ordering

More effort to align members on 4-byte boundary helps with
code size a tiny bit:

    text           data     bss     dec     hex filename
-1460454          60014    3656 1524124  17419c drivers/gpu/drm/i915/i915.ko
+1460254          60014    3656 1523924  1740d4 drivers/gpu/drm/i915/i915.ko

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170920092701.17963-3-tvrtko.ursulin@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5d65d0..4e2fcdd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -852,21 +852,27 @@ enum intel_platform {
 };
 
 struct intel_device_info {
-       u32 display_mmio_offset;
        u16 device_id;
-       u8 num_pipes;
-       u8 num_sprites[I915_MAX_PIPES];
-       u8 num_scalers[I915_MAX_PIPES];
-       u8 gen;
        u16 gen_mask;
-       enum intel_platform platform;
+
+       u8 gen;
        u8 gt; /* GT number, 0 if undefined */
-       u8 ring_mask; /* Rings supported by the HW */
        u8 num_rings;
+       u8 ring_mask; /* Rings supported by the HW */
+
+       enum intel_platform platform;
+
+       u32 display_mmio_offset;
+
+       u8 num_pipes;
+       u8 num_sprites[I915_MAX_PIPES];
+       u8 num_scalers[I915_MAX_PIPES];
+
 #define DEFINE_FLAG(name) u8 name:1
        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
        u16 ddb_size; /* in blocks */
+
        /* Register offsets for the various display pipes and transcoders */
        int pipe_offsets[I915_MAX_TRANSCODERS];
        int trans_offsets[I915_MAX_TRANSCODERS];