drm/amdgpu: expose only the first UVD instance for now

Going to completely rework the context to ring mapping with Nayan's GSoC
work, but for now just stopping to expose the second UVD instance should
do it.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 053d310..c7dce14 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -286,7 +286,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
        struct drm_crtc *crtc;
        uint32_t ui32 = 0;
        uint64_t ui64 = 0;
-       int i, j, found;
+       int i, found;
        int ui32_size = sizeof(ui32);
 
        if (!info->return_size || !info->return_pointer)
@@ -348,8 +348,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                        break;
                case AMDGPU_HW_IP_UVD:
                        type = AMD_IP_BLOCK_TYPE_UVD;
-                       for (i = 0; i < adev->uvd.num_uvd_inst; i++)
-                               ring_mask |= adev->uvd.inst[i].ring.ready << i;
+                       ring_mask |= adev->uvd.inst[0].ring.ready;
                        ib_start_alignment = 64;
                        ib_size_alignment = 64;
                        break;
@@ -362,11 +361,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                        break;
                case AMDGPU_HW_IP_UVD_ENC:
                        type = AMD_IP_BLOCK_TYPE_UVD;
-                       for (i = 0; i < adev->uvd.num_uvd_inst; i++)
-                               for (j = 0; j < adev->uvd.num_enc_rings; j++)
-                                       ring_mask |=
-                                       adev->uvd.inst[i].ring_enc[j].ready <<
-                                       (j + i * adev->uvd.num_enc_rings);
+                       for (i = 0; i < adev->uvd.num_enc_rings; i++)
+                               ring_mask |=
+                                       adev->uvd.inst[0].ring_enc[i].ready << i;
                        ib_start_alignment = 64;
                        ib_size_alignment = 64;
                        break;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index ea9850c..d835729 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -66,8 +66,6 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
                               u32 ring,
                               struct amdgpu_ring **out_ring)
 {
-       u32 instance;
-
        switch (mapper->hw_ip) {
        case AMDGPU_HW_IP_GFX:
                *out_ring = &adev->gfx.gfx_ring[ring];
@@ -79,16 +77,13 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
                *out_ring = &adev->sdma.instance[ring].ring;
                break;
        case AMDGPU_HW_IP_UVD:
-               instance = ring;
-               *out_ring = &adev->uvd.inst[instance].ring;
+               *out_ring = &adev->uvd.inst[0].ring;
                break;
        case AMDGPU_HW_IP_VCE:
                *out_ring = &adev->vce.ring[ring];
                break;
        case AMDGPU_HW_IP_UVD_ENC:
-               instance = ring / adev->uvd.num_enc_rings;
-               *out_ring =
-               &adev->uvd.inst[instance].ring_enc[ring%adev->uvd.num_enc_rings];
+               *out_ring = &adev->uvd.inst[0].ring_enc[ring];
                break;
        case AMDGPU_HW_IP_VCN_DEC:
                *out_ring = &adev->vcn.ring_dec;