In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184703
91177308-0d34-0410-b5e6-
96231b3b80d8
return;
}
- // Thumb1 NOP
- if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
- MI->getOperand(1).getReg() == ARM::R8) {
- O << "\tnop";
- printPredicateOperand(MI, 2, O);
- printAnnotation(O, Annot);
- return;
- }
-
// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
// a single GPRPair reg operand is used in the .td file to replace the two
nop
-@ CHECK-V6: nop @ encoding: [0xc0,0x46]
+@ CHECK-V6: mov r8, r8 @ encoding: [0xc0,0x46]
@ CHECK-V7: nop @ encoding: [0x00,0xbf]
@ CHECK: bkpt #2 @ encoding: [0x02,0xbe]
nop
-@ CHECK: nop @ encoding: [0xc0,0x46]
+@ CHECK: mov r8, r8 @ encoding: [0xc0,0x46]
cpsie aif
@ CHECK: cpsie aif @ encoding: [0x67,0xb6]
#------------------------------------------------------------------------------
# CHECK: mov r3, r4
# CHECK: movs r1, r3
+# CHECK: mov r8, r8
0x23 0x46
0x19 0x00
+0xc0 0x46
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
-# NOP
-#------------------------------------------------------------------------------
-# CHECK: nop
-
-0xc0 0x46
-
-
-#------------------------------------------------------------------------------
# ORR
#------------------------------------------------------------------------------
# CHECK: orrs r3, r4