ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'

The clock which was named as 'pll_clk' is actually not the clock source
of PLL in MIPI DSI. This patch fixes this disagreement.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e20cdc2..1538d7a 100644 (file)
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -167,7 +167,7 @@
                phys = <&mipi_phy 1>;
                phy-names = "dsim";
                clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
-               clock-names = "bus_clk", "pll_clk";
+               clock-names = "bus_clk", "sclk_mipi";
                status = "disabled";
                #address-cells = <1>;
                #size-cells = <0>;