store inst ok.

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index a1b03b4..a274ac2 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -207,12 +207,15 @@ signal reg_status   : std_logic_vector (7 downto 0);
 signal reg_pc_l     : std_logic_vector (7 downto 0);\r
 signal reg_pc_h     : std_logic_vector (7 downto 0);\r
 \r
---tmp acc carry/overflow reg.\r
+--tmp flag reg.\r
 signal reg_tmp_carry    : std_logic;\r
 signal reg_tmp_ovf      : std_logic;\r
 signal reg_tmp_condition    : std_logic;\r
 signal reg_tmp_pg_crossed   : std_logic;\r
 \r
+--tmp address reg.\r
+signal reg_tmp_l    : std_logic_vector (7 downto 0);\r
+signal reg_tmp_h    : std_logic_vector (7 downto 0);\r
 \r
 --bus i/o reg.\r
 signal reg_r_nw     : std_logic;\r
@@ -1114,7 +1117,139 @@ end;
                     pc_inc;\r
                 end if;\r
 \r
-           --jsr.\r
+           --a3 instructions.\r
+           --sta, stx, sty\r
+            elsif (reg_main_state = ST_A33_T2 or\r
+                reg_main_state = ST_A35_T2\r
+                ) then\r
+                --zp xy\r
+                --ind, x\r
+                --discarded cycle.\r
+                reg_addr    <= "00000000" & reg_idl_l;\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+            elsif (reg_main_state = ST_A33_T3) then\r
+                --ind, x\r
+                --bal + x cycle.\r
+                reg_addr    <= "00000000" & reg_idl_l;\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+            elsif (reg_main_state = ST_A33_T4) then\r
+                --ind, x\r
+                --bal + x + 1 cycle.\r
+                reg_addr    <= "00000000" & (reg_idl_l + 1);\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+            elsif (reg_main_state = ST_A34_T3) then\r
+                --abs xy\r
+                --discarded cycle.\r
+                if (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
+                    --sta, x\r
+                    reg_addr    <= reg_idl_h & (reg_idl_l + reg_x);\r
+                    calc_adl    := ("0" & reg_idl_l) + ("0" & reg_x);\r
+                elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then\r
+                    --sta, y\r
+                    reg_addr    <= reg_idl_h & (reg_idl_l + reg_y);\r
+                    calc_adl    := ("0" & reg_idl_l) + ("0" & reg_y);\r
+                end if;\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+\r
+                reg_tmp_pg_crossed <= calc_adl(8);\r
+            elsif (reg_main_state = ST_A36_T2) then\r
+                --ind, y\r
+                --ial cycle.\r
+                reg_addr    <= "00000000" & reg_idl_l;\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+            elsif (reg_main_state = ST_A36_T3) then\r
+                --ind, y\r
+                --ial + 1 cycle.\r
+                reg_addr    <= "00000000" & (reg_idl_l + 1);\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+            elsif (reg_main_state = ST_A36_T4) then\r
+                --ind, y\r
+                --bal + y cycle.\r
+                reg_addr    <= reg_tmp_h & (reg_tmp_l + reg_y);\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+                calc_adl    := ("0" & reg_tmp_l) + ("0" & reg_y);\r
+                reg_tmp_pg_crossed <= calc_adl(8);\r
+\r
+            elsif (reg_main_state = ST_A31_T2 or\r
+                reg_main_state = ST_A32_T3 or\r
+                reg_main_state = ST_A33_T5 or\r
+                reg_main_state = ST_A34_T4 or\r
+                reg_main_state = ST_A35_T3 or\r
+                reg_main_state = ST_A36_T5\r
+            ) then\r
+                --store cycle.\r
+                --data out\r
+                if (reg_inst(1 downto 0) = "01" and reg_inst(7 downto 5) = "100") then\r
+                    --sta\r
+                    reg_d_out   <= reg_acc;\r
+                elsif (reg_inst(1 downto 0) = "10" and reg_inst(7 downto 5) = "100") then\r
+                    --stx\r
+                    reg_d_out   <= reg_x;\r
+                elsif (reg_inst(1 downto 0) = "00" and reg_inst(7 downto 5) = "100") then\r
+                    --sty\r
+                    reg_d_out   <= reg_y;\r
+                end if;\r
+\r
+                --rw ctrl\r
+                if (reg_sub_state = ST_SUB32 or\r
+                    reg_sub_state = ST_SUB33 or\r
+                    reg_sub_state = ST_SUB40 or\r
+                    reg_sub_state = ST_SUB41\r
+                    ) then\r
+                    reg_r_nw    <= '0';\r
+                else\r
+                    reg_r_nw    <= 'Z';\r
+                end if;\r
+\r
+                --address bus out.\r
+                if (reg_main_state = ST_A31_T2) then\r
+                    --zp\r
+                    reg_addr    <= "00000000" & reg_idl_l;\r
+\r
+                elsif (reg_main_state = ST_A32_T3) then\r
+                    --abs\r
+                    reg_addr    <= reg_idl_h & reg_idl_l;\r
+\r
+                elsif (reg_main_state = ST_A33_T5) then\r
+                    --ind, x\r
+                    reg_addr    <= reg_tmp_h & reg_tmp_l;\r
+\r
+                elsif (reg_main_state = ST_A34_T4) then\r
+                    --abs xy\r
+                    if (reg_inst = conv_std_logic_vector(16#9d#, 8)) then\r
+                        --sta, x\r
+                        reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_x);\r
+                    elsif (reg_inst = conv_std_logic_vector(16#99#, 8)) then\r
+                        --sta, y\r
+                        reg_addr    <= (reg_idl_h + reg_tmp_pg_crossed) & (reg_idl_l + reg_y);\r
+                    end if;\r
+\r
+                elsif (reg_main_state = ST_A35_T3) then\r
+                    --zp xy\r
+                    --sta and sty has index x access,\r
+                    --stx has index y access.\r
+                    if (reg_inst = conv_std_logic_vector(16#95#, 8) or --sta\r
+                        reg_inst = conv_std_logic_vector(16#94#, 8) --sty\r
+                    ) then\r
+                        reg_addr    <= "00000000" & (reg_idl_l + reg_x);\r
+                    elsif (reg_inst = conv_std_logic_vector(16#96#, 8)) then\r
+                        --stx\r
+                        reg_addr    <= "00000000" & (reg_idl_l + reg_y);\r
+                    end if;\r
+\r
+                elsif (reg_main_state = ST_A36_T5) then\r
+                    --ind y\r
+                    reg_addr    <= (reg_tmp_h + reg_tmp_pg_crossed) & (reg_tmp_l + reg_y);\r
+                end if;\r
+\r
+            --jsr.\r
             elsif (reg_main_state = ST_A53_T2) then\r
                 --sp out (discarded.)\r
                 reg_addr    <= "00000001" & reg_sp;\r
@@ -1235,6 +1370,8 @@ end;
         if (pi_rst_n = '0') then\r
             reg_idl_l <= (others => '0');\r
             reg_idl_h <= (others => '0');\r
+            reg_tmp_l <= (others => '0');\r
+            reg_tmp_h <= (others => '0');\r
         elsif (rising_edge(pi_base_clk)) then\r
             if (reg_main_state = ST_A21_T1 or\r
                 reg_main_state = ST_A22_T1 or\r
@@ -1274,6 +1411,22 @@ end;
                     --get high data from rom.\r
                     reg_idl_h <= reg_d_in;\r
                 end if;\r
+            elsif (reg_main_state = ST_A33_T3 or\r
+                reg_main_state = ST_A36_T2\r
+                ) then\r
+                --a33 indr, x\r
+                --a33 indr, y\r
+                if (reg_sub_state = ST_SUB30) then\r
+                    reg_tmp_l <= reg_d_in;\r
+                end if;\r
+            elsif (reg_main_state = ST_A33_T4 or\r
+                reg_main_state = ST_A36_T3\r
+                ) then\r
+                --a33 indr, x\r
+                --a33 indr, y\r
+                if (reg_sub_state = ST_SUB30) then\r
+                    reg_tmp_h <= reg_d_in;\r
+                end if;\r
             end if;--if (reg_main_state = ST_RS_T0)\r
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
@@ -1309,6 +1462,7 @@ end;
     end process;\r
 \r
     --calcuration process...\r
+    --update acc, x, y, status registers.\r
     calc_p : process (pi_rst_n, pi_base_clk)\r
 \r
     variable calc_res : std_logic_vector (8 downto 0);\r